Lines Matching defs:dwmac
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
70 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
79 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
89 pr_debug("imx dwmac doesn't support %d interface\n",
95 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
110 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
127 dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
133 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
139 struct imx_priv_data *dwmac = priv;
143 ret = clk_prepare_enable(dwmac->clk_mem);
145 dev_err(dwmac->dev, "mem clock enable failed\n");
149 ret = clk_prepare_enable(dwmac->clk_tx);
151 dev_err(dwmac->dev, "tx clock enable failed\n");
152 clk_disable_unprepare(dwmac->clk_mem);
156 clk_disable_unprepare(dwmac->clk_tx);
157 clk_disable_unprepare(dwmac->clk_mem);
166 struct imx_priv_data *dwmac = priv;
169 plat_dat = dwmac->plat_dat;
171 if (dwmac->ops->set_intf_mode) {
172 ret = dwmac->ops->set_intf_mode(plat_dat);
188 struct imx_priv_data *dwmac = priv;
192 plat_dat = dwmac->plat_dat;
194 if (dwmac->ops->mac_rgmii_txclk_auto_adj ||
210 dev_err(dwmac->dev, "invalid speed %u\n", speed);
214 err = clk_set_rate(dwmac->clk_tx, rate);
216 dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
221 struct imx_priv_data *dwmac = priv;
227 if (!dwmac || mode != MLO_AN_FIXED)
230 if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
237 old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
239 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
241 writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
244 readl(dwmac->base_addr + MAC_CTRL_REG);
248 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
251 writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
274 imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
279 dwmac->rmii_refclk_ext = of_property_read_bool(np, "snps,rmii_refclk_ext");
281 dwmac->clk_tx = devm_clk_get(dev, "tx");
282 if (IS_ERR(dwmac->clk_tx)) {
284 return PTR_ERR(dwmac->clk_tx);
287 dwmac->clk_mem = NULL;
291 dwmac->clk_mem = devm_clk_get(dev, "mem");
292 if (IS_ERR(dwmac->clk_mem)) {
294 return PTR_ERR(dwmac->clk_mem);
304 dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");
305 if (IS_ERR(dwmac->intf_regmap))
306 return PTR_ERR(dwmac->intf_regmap);
308 err = of_property_read_u32_index(np, "intf_mode", 1, &dwmac->intf_reg_off);
322 struct imx_priv_data *dwmac;
330 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
331 if (!dwmac)
345 dwmac->ops = data;
346 dwmac->dev = &pdev->dev;
348 ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);
357 plat_dat->host_dma_width = dwmac->ops->addr_width;
362 plat_dat->bsp_priv = dwmac;
363 dwmac->plat_dat = plat_dat;
364 dwmac->base_addr = stmmac_res.addr;
366 ret = imx_dwmac_clks_config(dwmac, true);
370 ret = imx_dwmac_init(pdev, dwmac);
374 if (dwmac->ops->fix_mac_speed)
375 plat_dat->fix_mac_speed = dwmac->ops->fix_mac_speed;
376 dwmac->plat_dat->fix_soc_reset = dwmac->ops->fix_soc_reset;
387 imx_dwmac_clks_config(dwmac, false);
417 { .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
418 { .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
419 { .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },
428 .name = "imx-dwmac",