Lines Matching refs:netsec_write
331 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
385 netsec_write(priv, MAC_REG_DATA, value);
386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
560 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
562 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
564 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
565 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
572 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
574 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
576 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
577 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
776 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts);
1092 netsec_write(priv, NETSEC_REG_INTEN_SET,
1194 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
1362 netsec_write(priv, reg, readl(ucode + i * 4));
1408 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1410 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1422 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1423 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1424 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1430 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1432 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1435 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1437 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1441 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1443 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1457 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1458 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1468 netsec_write(priv, NETSEC_REG_TOP_STATUS,
1476 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1477 netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1484 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1487 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1517 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1521 netsec_write(priv, MAC_REG_DESC_INIT, 1);
1548 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1549 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1571 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1572 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1598 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1602 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1606 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1662 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1684 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
2174 netsec_write(priv, NETSEC_REG_CLK_EN, 0);
2187 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |