Lines Matching refs:pd
86 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
88 return ioread32(pd->ioaddr + offset);
92 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
94 iowrite32(value, pd->ioaddr + offset);
97 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
100 smsc9420_reg_read(pd, ID_REV);
105 struct smsc9420_pdata *pd = bus->priv;
110 spin_lock_irqsave(&pd->phy_lock, flags);
113 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
114 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
121 smsc9420_reg_write(pd, MII_ACCESS, addr);
125 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
127 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
133 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
136 spin_unlock_irqrestore(&pd->phy_lock, flags);
143 struct smsc9420_pdata *pd = bus->priv;
148 spin_lock_irqsave(&pd->phy_lock, flags);
151 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
152 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
157 smsc9420_reg_write(pd, MII_DATA, (u32)val);
162 smsc9420_reg_write(pd, MII_ACCESS, addr);
166 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
174 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
177 spin_unlock_irqrestore(&pd->phy_lock, flags);
189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
193 BUG_ON(!pd);
195 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
196 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
200 smsc9420_reg_write(pd, E2P_CMD,
205 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
209 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
216 struct smsc9420_pdata *pd = netdev_priv(netdev);
219 strscpy(drvinfo->bus_info, pci_name(pd->pdev),
226 struct smsc9420_pdata *pd = netdev_priv(netdev);
227 return pd->msg_enable;
232 struct smsc9420_pdata *pd = netdev_priv(netdev);
233 pd->msg_enable = data;
246 struct smsc9420_pdata *pd = netdev_priv(dev);
251 regs->version = smsc9420_reg_read(pd, ID_REV);
253 data[j++] = smsc9420_reg_read(pd, i);
264 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
266 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
268 smsc9420_reg_write(pd, GPIO_CFG, temp);
272 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
277 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
278 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
279 netif_warn(pd, hw, pd->dev, "Busy at start\n");
284 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
288 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
292 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
297 netif_info(pd, hw, pd->dev,
305 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
311 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
312 ret = smsc9420_eeprom_send_cmd(pd, op);
315 data[address] = smsc9420_reg_read(pd, E2P_DATA);
320 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
326 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
327 ret = smsc9420_eeprom_send_cmd(pd, op);
331 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
332 ret = smsc9420_eeprom_send_cmd(pd, op);
346 struct smsc9420_pdata *pd = netdev_priv(dev);
350 smsc9420_eeprom_enable_access(pd);
354 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
370 struct smsc9420_pdata *pd = netdev_priv(dev);
376 smsc9420_eeprom_enable_access(pd);
377 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
378 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
379 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
406 struct smsc9420_pdata *pd = netdev_priv(dev);
412 smsc9420_reg_write(pd, ADDRH, mac_high16);
413 smsc9420_reg_write(pd, ADDRL, mac_low32);
418 struct smsc9420_pdata *pd = netdev_priv(dev);
424 netif_dbg(pd, probe, pd->dev,
429 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
430 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
441 netif_dbg(pd, probe, pd->dev,
447 netif_dbg(pd, probe, pd->dev,
453 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
459 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
461 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
465 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
471 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
474 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
477 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
479 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
480 smsc9420_pci_flush_write(pd);
483 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
484 smsc9420_reg_write(pd, MAC_CR, mac_cr);
485 smsc9420_pci_flush_write(pd);
488 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
492 BUG_ON(!pd->tx_ring);
494 if (!pd->tx_buffers)
498 struct sk_buff *skb = pd->tx_buffers[i].skb;
501 BUG_ON(!pd->tx_buffers[i].mapping);
502 dma_unmap_single(&pd->pdev->dev,
503 pd->tx_buffers[i].mapping, skb->len,
508 pd->tx_ring[i].status = 0;
509 pd->tx_ring[i].length = 0;
510 pd->tx_ring[i].buffer1 = 0;
511 pd->tx_ring[i].buffer2 = 0;
515 kfree(pd->tx_buffers);
516 pd->tx_buffers = NULL;
518 pd->tx_ring_head = 0;
519 pd->tx_ring_tail = 0;
522 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
526 BUG_ON(!pd->rx_ring);
528 if (!pd->rx_buffers)
532 if (pd->rx_buffers[i].skb)
533 dev_kfree_skb_any(pd->rx_buffers[i].skb);
535 if (pd->rx_buffers[i].mapping)
536 dma_unmap_single(&pd->pdev->dev,
537 pd->rx_buffers[i].mapping,
540 pd->rx_ring[i].status = 0;
541 pd->rx_ring[i].length = 0;
542 pd->rx_ring[i].buffer1 = 0;
543 pd->rx_ring[i].buffer2 = 0;
547 kfree(pd->rx_buffers);
548 pd->rx_buffers = NULL;
550 pd->rx_ring_head = 0;
551 pd->rx_ring_tail = 0;
554 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
560 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
562 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
563 smsc9420_pci_flush_write(pd);
566 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
567 smsc9420_reg_write(pd, MAC_CR, mac_cr);
568 smsc9420_pci_flush_write(pd);
571 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
573 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
574 smsc9420_pci_flush_write(pd);
578 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
584 netif_warn(pd, ifdown, pd->dev,
588 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
593 struct smsc9420_pdata *pd = dev_id;
598 BUG_ON(!pd);
599 BUG_ON(!pd->ioaddr);
601 int_cfg = smsc9420_reg_read(pd, INT_CFG);
608 int_sts = smsc9420_reg_read(pd, INT_STAT);
611 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
616 netif_wake_queue(pd->dev);
621 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
623 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
624 smsc9420_pci_flush_write(pd);
627 napi_schedule(&pd->napi);
631 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
638 spin_lock_irqsave(&pd->int_lock, flags);
639 int_ctl = smsc9420_reg_read(pd, INT_CTL);
641 smsc9420_reg_write(pd, INT_CTL, int_ctl);
642 spin_unlock_irqrestore(&pd->int_lock, flags);
644 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
645 pd->software_irq_signal = true;
652 smsc9420_pci_flush_write(pd);
660 struct smsc9420_pdata *pd = netdev_priv(dev);
661 const int irq = pd->pdev->irq;
669 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
671 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
672 smsc9420_reg_read(pd, BUS_MODE);
674 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
675 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
680 struct smsc9420_pdata *pd = netdev_priv(dev);
684 BUG_ON(!pd);
688 spin_lock_irqsave(&pd->int_lock, flags);
689 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
690 smsc9420_reg_write(pd, INT_CFG, int_cfg);
691 spin_unlock_irqrestore(&pd->int_lock, flags);
694 napi_disable(&pd->napi);
696 smsc9420_stop_tx(pd);
697 smsc9420_free_tx_ring(pd);
699 smsc9420_stop_rx(pd);
700 smsc9420_free_rx_ring(pd);
702 free_irq(pd->pdev->irq, pd);
704 smsc9420_dmac_soft_reset(pd);
709 mdiobus_unregister(pd->mii_bus);
710 mdiobus_free(pd->mii_bus);
739 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
742 struct net_device *dev = pd->dev;
750 if (pd->rx_csum)
756 dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
758 pd->rx_buffers[index].mapping = 0;
760 skb = pd->rx_buffers[index].skb;
761 pd->rx_buffers[index].skb = NULL;
763 if (pd->rx_csum) {
778 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
780 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
783 BUG_ON(pd->rx_buffers[index].skb);
784 BUG_ON(pd->rx_buffers[index].mapping);
789 mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
791 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
793 netif_warn(pd, rx_err, pd->dev, "dma_map_single failed!\n");
797 pd->rx_buffers[index].skb = skb;
798 pd->rx_buffers[index].mapping = mapping;
799 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
800 pd->rx_ring[index].status = RDES0_OWN_;
806 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
808 while (pd->rx_ring_tail != pd->rx_ring_head) {
809 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
812 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
818 struct smsc9420_pdata *pd =
820 struct net_device *dev = pd->dev;
826 status = pd->rx_ring[pd->rx_ring_head].status;
833 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
834 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
835 smsc9420_alloc_new_rx_buffers(pd);
838 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
843 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
844 smsc9420_pci_flush_write(pd);
847 napi_complete_done(&pd->napi, work_done);
850 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
852 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
853 smsc9420_pci_flush_write(pd);
889 struct smsc9420_pdata *pd = netdev_priv(dev);
891 while (pd->tx_ring_tail != pd->tx_ring_head) {
892 int index = pd->tx_ring_tail;
896 status = pd->tx_ring[index].status;
897 length = pd->tx_ring[index].length;
905 BUG_ON(!pd->tx_buffers[index].skb);
906 BUG_ON(!pd->tx_buffers[index].mapping);
908 dma_unmap_single(&pd->pdev->dev,
909 pd->tx_buffers[index].mapping,
910 pd->tx_buffers[index].skb->len,
912 pd->tx_buffers[index].mapping = 0;
914 dev_kfree_skb_any(pd->tx_buffers[index].skb);
915 pd->tx_buffers[index].skb = NULL;
917 pd->tx_ring[index].buffer1 = 0;
920 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
927 struct smsc9420_pdata *pd = netdev_priv(dev);
929 int index = pd->tx_ring_head;
932 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
937 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
938 BUG_ON(pd->tx_buffers[index].skb);
939 BUG_ON(pd->tx_buffers[index].mapping);
941 mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
943 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
944 netif_warn(pd, tx_err, pd->dev,
949 pd->tx_buffers[index].skb = skb;
950 pd->tx_buffers[index].mapping = mapping;
955 netif_stop_queue(pd->dev);
962 pd->tx_ring[index].buffer1 = mapping;
963 pd->tx_ring[index].length = tmp_desc1;
967 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
970 pd->tx_ring[index].status = TDES0_OWN_;
976 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
977 smsc9420_pci_flush_write(pd);
984 struct smsc9420_pdata *pd = netdev_priv(dev);
985 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
993 struct smsc9420_pdata *pd = netdev_priv(dev);
994 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
997 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
1002 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1010 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1021 smsc9420_reg_write(pd, HASHH, hash_hi);
1022 smsc9420_reg_write(pd, HASHL, hash_lo);
1028 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1029 smsc9420_reg_write(pd, HASHH, 0);
1030 smsc9420_reg_write(pd, HASHL, 0);
1037 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1038 smsc9420_pci_flush_write(pd);
1041 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1043 struct net_device *dev = pd->dev;
1057 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1061 netif_info(pd, link, pd->dev, "half duplex\n");
1065 smsc9420_reg_write(pd, FLOW, flow);
1072 struct smsc9420_pdata *pd = netdev_priv(dev);
1076 if (phy_dev->duplex != pd->last_duplex) {
1077 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1079 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1082 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1085 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1087 smsc9420_phy_update_flowcontrol(pd);
1088 pd->last_duplex = phy_dev->duplex;
1092 if (carrier != pd->last_carrier) {
1094 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1096 netif_dbg(pd, link, pd->dev, "no carrier\n");
1097 pd->last_carrier = carrier;
1103 struct smsc9420_pdata *pd = netdev_priv(dev);
1109 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1130 pd->last_duplex = -1;
1131 pd->last_carrier = -1;
1138 struct smsc9420_pdata *pd = netdev_priv(dev);
1141 pd->mii_bus = mdiobus_alloc();
1142 if (!pd->mii_bus) {
1146 pd->mii_bus->name = DRV_MDIONAME;
1147 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(pd->pdev));
1148 pd->mii_bus->priv = pd;
1149 pd->mii_bus->read = smsc9420_mii_read;
1150 pd->mii_bus->write = smsc9420_mii_write;
1153 pd->mii_bus->phy_mask = ~(1 << 1);
1155 if (mdiobus_register(pd->mii_bus)) {
1156 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1161 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1168 mdiobus_unregister(pd->mii_bus);
1170 mdiobus_free(pd->mii_bus);
1175 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1179 BUG_ON(!pd->tx_ring);
1181 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1184 if (!pd->tx_buffers)
1189 pd->tx_buffers[i].skb = NULL;
1190 pd->tx_buffers[i].mapping = 0;
1191 pd->tx_ring[i].status = 0;
1192 pd->tx_ring[i].length = 0;
1193 pd->tx_ring[i].buffer1 = 0;
1194 pd->tx_ring[i].buffer2 = 0;
1196 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1199 pd->tx_ring_head = 0;
1200 pd->tx_ring_tail = 0;
1202 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1203 smsc9420_pci_flush_write(pd);
1208 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1212 BUG_ON(!pd->rx_ring);
1214 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1217 if (pd->rx_buffers == NULL)
1222 pd->rx_ring[i].status = 0;
1223 pd->rx_ring[i].length = PKT_BUF_SZ;
1224 pd->rx_ring[i].buffer2 = 0;
1225 pd->rx_buffers[i].skb = NULL;
1226 pd->rx_buffers[i].mapping = 0;
1228 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1232 if (smsc9420_alloc_rx_buffer(pd, i)) {
1233 netif_warn(pd, ifup, pd->dev,
1239 pd->rx_ring_head = 0;
1240 pd->rx_ring_tail = 0;
1242 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1243 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1244 smsc9420_reg_read(pd, VLAN1));
1246 if (pd->rx_csum) {
1248 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1249 smsc9420_reg_write(pd, COE_CR, coe);
1250 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1253 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1254 smsc9420_pci_flush_write(pd);
1259 smsc9420_free_rx_ring(pd);
1266 struct smsc9420_pdata *pd = netdev_priv(dev);
1268 const int irq = pd->pdev->irq;
1273 netif_warn(pd, ifup, pd->dev,
1282 spin_lock_irqsave(&pd->int_lock, flags);
1283 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1284 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1285 smsc9420_reg_write(pd, INT_CTL, 0);
1286 spin_unlock_irqrestore(&pd->int_lock, flags);
1287 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1288 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1289 smsc9420_pci_flush_write(pd);
1291 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1293 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1298 smsc9420_dmac_soft_reset(pd);
1301 smsc9420_reg_write(pd, MAC_CR, 0);
1306 smsc9420_reg_write(pd, GPIO_CFG,
1315 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1317 smsc9420_pci_flush_write(pd);
1320 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1322 smsc9420_reg_write(pd, DMAC_CONTROL,
1325 smsc9420_pci_flush_write(pd);
1328 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1329 pd->software_irq_signal = false;
1331 spin_lock_irqsave(&pd->int_lock, flags);
1333 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1336 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1339 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1340 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1341 spin_unlock_irqrestore(&pd->int_lock, flags);
1342 smsc9420_pci_flush_write(pd);
1346 if (pd->software_irq_signal)
1352 spin_lock_irqsave(&pd->int_lock, flags);
1353 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1354 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1355 spin_unlock_irqrestore(&pd->int_lock, flags);
1357 if (!pd->software_irq_signal) {
1358 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1363 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1365 result = smsc9420_alloc_tx_ring(pd);
1367 netif_warn(pd, ifup, pd->dev,
1373 result = smsc9420_alloc_rx_ring(pd);
1375 netif_warn(pd, ifup, pd->dev,
1383 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1391 napi_enable(&pd->napi);
1394 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1395 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1397 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1399 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1400 smsc9420_pci_flush_write(pd);
1402 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1405 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1406 smsc9420_pci_flush_write(pd);
1410 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1413 spin_lock_irqsave(&pd->int_lock, flags);
1414 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1415 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1416 spin_unlock_irqrestore(&pd->int_lock, flags);
1421 smsc9420_free_rx_ring(pd);
1423 smsc9420_free_tx_ring(pd);
1425 free_irq(irq, pd);
1433 struct smsc9420_pdata *pd = netdev_priv(dev);
1438 spin_lock_irqsave(&pd->int_lock, flags);
1439 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1440 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1441 spin_unlock_irqrestore(&pd->int_lock, flags);
1445 smsc9420_stop_tx(pd);
1446 smsc9420_free_tx_ring(pd);
1448 napi_disable(&pd->napi);
1449 smsc9420_stop_rx(pd);
1450 smsc9420_free_rx_ring(pd);
1452 free_irq(pd->pdev->irq, pd);
1498 struct smsc9420_pdata *pd;
1514 dev = alloc_etherdev(sizeof(*pd));
1545 pd = netdev_priv(dev);
1548 pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1550 &pd->rx_dma_addr, GFP_KERNEL);
1552 if (!pd->rx_ring)
1556 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1557 pd->tx_dma_addr = pd->rx_dma_addr +
1560 pd->pdev = pdev;
1561 pd->dev = dev;
1562 pd->ioaddr = virt_addr;
1563 pd->msg_enable = smsc_debug;
1564 pd->rx_csum = true;
1566 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1568 id_rev = smsc9420_reg_read(pd, ID_REV);
1571 netif_info(pd, probe, pd->dev,
1575 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1576 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1580 smsc9420_dmac_soft_reset(pd);
1581 smsc9420_eeprom_reload(pd);
1587 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll);
1591 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1598 spin_lock_init(&pd->int_lock);
1599 spin_lock_init(&pd->phy_lock);
1608 pd->rx_ring, pd->rx_dma_addr);
1624 struct smsc9420_pdata *pd;
1630 pd = netdev_priv(dev);
1634 BUG_ON(pd->tx_buffers);
1635 BUG_ON(pd->rx_buffers);
1637 BUG_ON(!pd->tx_ring);
1638 BUG_ON(!pd->rx_ring);
1642 pd->rx_ring, pd->rx_dma_addr);
1644 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);