Lines Matching refs:outw
146 #define SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); }
262 #define set_bits(v, p) outw(inw(p)|(v), (p))
263 #define mask_bits(v, p) outw(inw(p)&(v), (p))
551 outw(MOT_EEPROM + i, ioaddr + POINTER);
553 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL);
775 outw(0, ioaddr + CONTROL);
1046 outw(save, ioaddr + BANK_SELECT);
1098 outw(0, ioaddr + INTERRUPT);
1105 outw(CTL_POWERDOWN, ioaddr + CONTROL );
1147 outw(packet_no, ioaddr + PNR_ARR);
1149 outw(PTR_AUTOINC , ioaddr + POINTER);
1160 outw(0, ioaddr + DATA_1);
1161 outw(length + 6, ioaddr + DATA_1);
1165 outw((length & 1) ? 0x2000 | buf[length-1] : 0, ioaddr + DATA_1);
1169 outw(((IM_TX_INT|IM_TX_EMPTY_INT)<<8) |
1174 outw(MC_ENQUEUE , ioaddr + MMU_CMD);
1237 outw(MC_RESET, ioaddr + MMU_CMD);
1242 outw(MC_ALLOC | num_pages, ioaddr + MMU_CMD);
1247 outw((ir&0xff00) | IM_ALLOC_INT, ioaddr + INTERRUPT);
1256 outw((IM_ALLOC_INT << 8) | (ir & 0xff00), ioaddr + INTERRUPT);
1277 outw(packet_no, ioaddr + PNR_ARR);
1280 outw(PTR_AUTOINC | PTR_READ | 0, ioaddr + POINTER);
1297 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1300 outw(MC_FREEPKT, ioaddr + MMU_CMD); /* Free the packet memory. */
1305 outw(saved_packet, ioaddr + PNR_ARR);
1332 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1336 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL);
1337 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1377 outw(0, ioaddr + INTERRUPT);
1394 outw(IM_TX_INT, ioaddr + INTERRUPT);
1398 outw(IM_TX_EMPTY_INT, ioaddr + INTERRUPT);
1420 outw(IM_RX_OVRN_INT, ioaddr + INTERRUPT);
1430 outw((mask<<8), ioaddr + INTERRUPT);
1431 outw(saved_pointer, ioaddr + POINTER);
1488 outw(PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + POINTER);
1506 outw(MC_RELEASE, ioaddr + MMU_CMD);
1532 outw(MC_RELEASE, ioaddr + MMU_CMD);
1579 outw(rx_cfg_setting, ioaddr + RCR);
1624 outw(smc->cfg | CFG_AUI_SELECT, ioaddr + CONFIG);
1630 outw(smc->cfg, ioaddr + CONFIG);
1651 outw(RCR_SOFTRESET, ioaddr + RCR);
1655 outw(RCR_CLEAR, ioaddr + RCR);
1656 outw(TCR_CLEAR, ioaddr + TCR);
1663 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1668 outw((dev->if_port == 2 ? OSI_AUI_PWR : 0) |
1674 outw((dev->dev_addr[i+1]<<8)+dev->dev_addr[i],
1679 outw(MC_RESET, ioaddr + MMU_CMD);
1680 outw(0, ioaddr + INTERRUPT);
1684 outw(((smc->cfg & CFG_MII_SELECT) ? 0 : TCR_MONCSN) |
1704 outw((IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT) << 8,
1734 outw(MC_RESET, ioaddr + MMU_CMD);
1791 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR);
1898 outw(tmp, ioaddr + TCR);