Lines Matching defs:base
106 void __iomem *base;
236 #define RCR_CLEAR 0x0 /* set it to a base state */
387 readb(smc->base+MEGAHERTZ_ISR);
389 readb(smc->base+MEGAHERTZ_ISR);
395 tmp = readb(smc->base + link->config_base + CISREG_COR);
397 writeb(tmp, smc->base + link->config_base + CISREG_COR);
447 smc->base = ioremap(link->resource[2]->start,
525 /* Set UART base address and force map with COR bit 1 */
526 writeb(iouart & 0xff, smc->base + MOT_UART + CISREG_IOBASE_0);
527 writeb((iouart >> 8) & 0xff, smc->base + MOT_UART + CISREG_IOBASE_1);
528 writeb(MOT_NORMAL, smc->base + MOT_UART + CISREG_COR);
530 /* Set SMC base address and force map with COR bit 1 */
531 writeb(ioaddr & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_0);
532 writeb((ioaddr >> 8) & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_1);
533 writeb(MOT_NORMAL, smc->base + MOT_LAN + CISREG_COR);
962 iounmap(smc->base);
1446 cor = readb(smc->base + MOT_UART + CISREG_COR);
1447 writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_UART + CISREG_COR);
1448 writeb(cor, smc->base + MOT_UART + CISREG_COR);
1449 cor = readb(smc->base + MOT_LAN + CISREG_COR);
1450 writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_LAN + CISREG_COR);
1451 writeb(cor, smc->base + MOT_LAN + CISREG_COR);
1454 if ((smc->base != NULL) && /* Megahertz MFC's */
1459 tmp = readb(smc->base+MEGAHERTZ_ISR);
1460 tmp = readb(smc->base+MEGAHERTZ_ISR);
1463 writeb(tmp, smc->base + MEGAHERTZ_ISR);
1464 writeb(tmp, smc->base + MEGAHERTZ_ISR);
1659 No point in writing the I/O base register ;-> */
1861 ecmd->base.port = (tmp & CFG_AUI_SELECT) ? PORT_AUI : PORT_TP;
1862 ecmd->base.speed = SPEED_10;
1863 ecmd->base.phy_address = ioaddr + MGMT;
1867 ecmd->base.duplex = (tmp & TCR_FDUPLX) ? DUPLEX_FULL : DUPLEX_HALF;
1879 if (ecmd->base.speed != SPEED_10)
1881 if (ecmd->base.duplex != DUPLEX_HALF &&
1882 ecmd->base.duplex != DUPLEX_FULL)
1884 if (ecmd->base.port != PORT_TP && ecmd->base.port != PORT_AUI)
1887 if (ecmd->base.port == PORT_AUI)
1894 if (ecmd->base.duplex == DUPLEX_FULL)