Lines Matching defs:sr32
211 #define sr32(reg) ioread32(ioaddr + (reg))
342 rfcrSave = sr32(rfcr);
389 if (sr32(mear) & EEGNT) {
550 sw32(cr, ACCESSMODE | sr32(cr));
577 ret = (sr32(CFGPMC) & PMESP) >> 27;
812 #define eeprom_delay() sr32(mear)
852 retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);
866 #define mdio_delay() sr32(mear)
926 retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);
1071 sw32(cr, RxENA | sr32(cr));
1101 rfcrSave = sr32(rfcr);
1115 net_dev->name, i, sr32(rfdr));
1153 net_dev->name, sr32(txdp));
1214 net_dev->name, sr32(rxdp));
1385 sw32(cfg, ~EXD & sr32(cfg));
1389 sw32(cfg, EXD | sr32(cfg));
1415 if (sr32( cfg) & EDB_MASTER_EN) {
1558 net_dev->name, sr32(cr), sr32(isr));
1636 sw32(cr, TxENA | sr32(cr));
1689 status = sr32(isr);
1724 net_dev->name, sr32(isr));
1886 sw32(cr , RxENA | sr32(cr));
1984 sw32(cr, RxDIS | TxDIS | sr32(cr));
2134 pmctrl_bits = sr32(pmctrl);
2162 if (sr32(mear) & EEGNT) {
2437 cr_saved = sr32(cr);
2440 sw32(txcfg, sr32(txcfg) | TxMLB);
2441 sw32(rxcfg, sr32(rxcfg) | RxATX);
2467 sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));
2471 status ^= sr32(isr) & status;
2522 sw32(cr, RxDIS | TxDIS | sr32(cr));
2551 sw32(cr, RxENA | sr32(cr));