Lines Matching defs:sis_priv
259 struct sis900_private *sis_priv = netdev_priv(net_dev);
260 void __iomem *ioaddr = sis_priv->ioaddr;
336 struct sis900_private *sis_priv = netdev_priv(net_dev);
337 void __iomem *ioaddr = sis_priv->ioaddr;
382 struct sis900_private *sis_priv = netdev_priv(net_dev);
383 void __iomem *ioaddr = sis_priv->ioaddr;
435 struct sis900_private *sis_priv;
482 sis_priv = netdev_priv(net_dev);
483 sis_priv->ioaddr = ioaddr;
484 sis_priv->pci_dev = pci_dev;
485 spin_lock_init(&sis_priv->lock);
487 sis_priv->eeprom_size = 24;
497 sis_priv->tx_ring = ring_space;
498 sis_priv->tx_ring_dma = ring_dma;
506 sis_priv->rx_ring = ring_space;
507 sis_priv->rx_ring_dma = ring_dma;
515 sis_priv->msg_enable = sis900_debug;
517 sis_priv->msg_enable = SIS900_DEF_MSG;
519 sis_priv->mii_info.dev = net_dev;
520 sis_priv->mii_info.mdio_read = mdio_read;
521 sis_priv->mii_info.mdio_write = mdio_write;
522 sis_priv->mii_info.phy_id_mask = 0x1f;
523 sis_priv->mii_info.reg_num_mask = 0x1f;
526 sis_priv->chipset_rev = pci_dev->revision;
527 if(netif_msg_probe(sis_priv))
530 dev_name, sis_priv->chipset_rev);
533 if (sis_priv->chipset_rev == SIS630E_900_REV)
535 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
537 else if (sis_priv->chipset_rev == SIS96x_900_REV)
549 if (sis_priv->chipset_rev == SIS630ET_900_REV)
563 sis_priv->host_bridge_rev = dev->revision;
578 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
584 dma_free_coherent(&pci_dev->dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
585 sis_priv->rx_ring_dma);
587 dma_free_coherent(&pci_dev->dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
588 sis_priv->tx_ring_dma);
607 struct sis900_private *sis_priv = netdev_priv(net_dev);
608 const char *dev_name = pci_name(sis_priv->pci_dev);
613 sis_priv->mii = NULL;
626 if (netif_msg_probe(sis_priv))
634 mii_phy = sis_priv->first_mii;
648 mii_phy->next = sis_priv->mii;
649 sis_priv->mii = mii_phy;
650 sis_priv->first_mii = mii_phy;
674 if (sis_priv->mii == NULL) {
680 sis_priv->mii = NULL;
684 if ((sis_priv->mii->phy_id0 == 0x001D) &&
685 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
686 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
689 if ((sis_priv->mii->phy_id0 == 0x0015) &&
690 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
691 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
697 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
706 if (sis_priv->chipset_rev == SIS630E_900_REV) {
708 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
709 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
710 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
711 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
712 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
715 if (sis_priv->mii->status & MII_STAT_LINK)
734 struct sis900_private *sis_priv = netdev_priv(net_dev);
739 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
763 default_phy = sis_priv->first_mii;
765 if (sis_priv->mii != default_phy) {
766 sis_priv->mii = default_phy;
767 sis_priv->cur_phy = default_phy->phy_addr;
769 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
772 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
774 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
777 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
778 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
779 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1042 struct sis900_private *sis_priv = netdev_priv(net_dev);
1043 void __iomem *ioaddr = sis_priv->ioaddr;
1050 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1052 ret = request_irq(sis_priv->pci_dev->irq, sis900_interrupt, IRQF_SHARED,
1067 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1074 sis900_check_mode(net_dev, sis_priv->mii);
1078 timer_setup(&sis_priv->timer, sis900_timer, 0);
1079 sis_priv->timer.expires = jiffies + HZ;
1080 add_timer(&sis_priv->timer);
1096 struct sis900_private *sis_priv = netdev_priv(net_dev);
1097 void __iomem *ioaddr = sis_priv->ioaddr;
1113 if (netif_msg_hw(sis_priv)) {
1133 struct sis900_private *sis_priv = netdev_priv(net_dev);
1134 void __iomem *ioaddr = sis_priv->ioaddr;
1137 sis_priv->tx_full = 0;
1138 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1141 sis_priv->tx_skbuff[i] = NULL;
1143 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1145 sis_priv->tx_ring[i].cmdsts = 0;
1146 sis_priv->tx_ring[i].bufptr = 0;
1150 sw32(txdp, sis_priv->tx_ring_dma);
1151 if (netif_msg_hw(sis_priv))
1167 struct sis900_private *sis_priv = netdev_priv(net_dev);
1168 void __iomem *ioaddr = sis_priv->ioaddr;
1171 sis_priv->cur_rx = 0;
1172 sis_priv->dirty_rx = 0;
1176 sis_priv->rx_skbuff[i] = NULL;
1178 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1180 sis_priv->rx_ring[i].cmdsts = 0;
1181 sis_priv->rx_ring[i].bufptr = 0;
1195 sis_priv->rx_skbuff[i] = skb;
1196 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1197 sis_priv->rx_ring[i].bufptr = dma_map_single(&sis_priv->pci_dev->dev,
1201 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1202 sis_priv->rx_ring[i].bufptr))) {
1204 sis_priv->rx_skbuff[i] = NULL;
1208 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1211 sw32(rxdp, sis_priv->rx_ring_dma);
1212 if (netif_msg_hw(sis_priv))
1246 struct sis900_private *sis_priv = netdev_priv(net_dev);
1255 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1256 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1260 sis_priv->cur_phy, MII_RESV)) >> 3;
1282 (sis_priv->host_bridge_rev == SIS630B0 ||
1283 sis_priv->host_bridge_rev == SIS630B1)) {
1290 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1293 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1295 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1297 (sis_priv->host_bridge_rev == SIS630B0 ||
1298 sis_priv->host_bridge_rev == SIS630B1))
1299 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1302 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1317 struct sis900_private *sis_priv = from_timer(sis_priv, t, timer);
1318 struct net_device *net_dev = sis_priv->mii_info.dev;
1319 struct mii_phy *mii_phy = sis_priv->mii;
1324 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1325 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1332 mii_phy = sis_priv->mii;
1339 sis900_set_mode(sis_priv, speed, duplex);
1340 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1348 if(netif_msg_link(sis_priv))
1354 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1356 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1362 sis_priv->timer.expires = jiffies + next_tick;
1363 add_timer(&sis_priv->timer);
1380 struct sis900_private *sis_priv = netdev_priv(net_dev);
1381 void __iomem *ioaddr = sis_priv->ioaddr;
1387 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1392 sis900_set_mode(sis_priv, speed, duplex);
1393 sis_priv->autong_complete = 1;
1460 struct sis900_private *sis_priv = netdev_priv(net_dev);
1468 if(netif_msg_link(sis_priv))
1470 sis_priv->autong_complete = 1;
1478 sis_priv->autong_complete = 0;
1495 struct sis900_private *sis_priv = netdev_priv(net_dev);
1496 struct mii_phy *phy = sis_priv->mii;
1497 int phy_addr = sis_priv->cur_phy;
1521 sis_priv->autong_complete = 1;
1531 if(netif_msg_link(sis_priv))
1551 struct sis900_private *sis_priv = netdev_priv(net_dev);
1552 void __iomem *ioaddr = sis_priv->ioaddr;
1556 if (netif_msg_tx_err(sis_priv)) {
1565 spin_lock_irqsave(&sis_priv->lock, flags);
1568 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1570 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1573 dma_unmap_single(&sis_priv->pci_dev->dev,
1574 sis_priv->tx_ring[i].bufptr,
1577 sis_priv->tx_skbuff[i] = NULL;
1578 sis_priv->tx_ring[i].cmdsts = 0;
1579 sis_priv->tx_ring[i].bufptr = 0;
1583 sis_priv->tx_full = 0;
1586 spin_unlock_irqrestore(&sis_priv->lock, flags);
1591 sw32(txdp, sis_priv->tx_ring_dma);
1610 struct sis900_private *sis_priv = netdev_priv(net_dev);
1611 void __iomem *ioaddr = sis_priv->ioaddr;
1617 spin_lock_irqsave(&sis_priv->lock, flags);
1620 entry = sis_priv->cur_tx % NUM_TX_DESC;
1621 sis_priv->tx_skbuff[entry] = skb;
1624 sis_priv->tx_ring[entry].bufptr = dma_map_single(&sis_priv->pci_dev->dev,
1627 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1628 sis_priv->tx_ring[entry].bufptr))) {
1630 sis_priv->tx_skbuff[entry] = NULL;
1632 spin_unlock_irqrestore(&sis_priv->lock, flags);
1635 sis_priv->tx_ring[entry].cmdsts = (OWN | INTR | skb->len);
1638 sis_priv->cur_tx ++;
1639 index_cur_tx = sis_priv->cur_tx;
1640 index_dirty_tx = sis_priv->dirty_tx;
1647 sis_priv->tx_full = 1;
1654 sis_priv->tx_full = 1;
1658 spin_unlock_irqrestore(&sis_priv->lock, flags);
1660 if (netif_msg_tx_queued(sis_priv))
1680 struct sis900_private *sis_priv = netdev_priv(net_dev);
1682 void __iomem *ioaddr = sis_priv->ioaddr;
1686 spin_lock (&sis_priv->lock);
1707 if(netif_msg_intr(sis_priv))
1713 if(netif_msg_intr(sis_priv))
1721 if(netif_msg_intr(sis_priv))
1726 spin_unlock (&sis_priv->lock);
1742 struct sis900_private *sis_priv = netdev_priv(net_dev);
1743 void __iomem *ioaddr = sis_priv->ioaddr;
1744 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1745 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1748 if (netif_msg_rx_status(sis_priv))
1751 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1752 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1772 if (netif_msg_rx_err(sis_priv))
1786 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1791 dma_unmap_single(&sis_priv->pci_dev->dev,
1792 sis_priv->rx_ring[entry].bufptr,
1804 skb = sis_priv->rx_skbuff[entry];
1812 if (sis_priv->rx_skbuff[entry] == NULL) {
1813 if (netif_msg_rx_err(sis_priv))
1817 net_dev->name, sis_priv->cur_rx,
1818 sis_priv->dirty_rx);
1824 rx_skb = sis_priv->rx_skbuff[entry];
1834 sis_priv->dirty_rx++;
1836 sis_priv->rx_skbuff[entry] = skb;
1837 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1838 sis_priv->rx_ring[entry].bufptr =
1839 dma_map_single(&sis_priv->pci_dev->dev,
1842 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1843 sis_priv->rx_ring[entry].bufptr))) {
1845 sis_priv->rx_skbuff[entry] = NULL;
1849 sis_priv->cur_rx++;
1850 entry = sis_priv->cur_rx % NUM_RX_DESC;
1851 rx_status = sis_priv->rx_ring[entry].cmdsts;
1856 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1859 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1861 if (sis_priv->rx_skbuff[entry] == NULL) {
1871 sis_priv->rx_skbuff[entry] = skb;
1872 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1873 sis_priv->rx_ring[entry].bufptr =
1874 dma_map_single(&sis_priv->pci_dev->dev,
1877 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1878 sis_priv->rx_ring[entry].bufptr))) {
1880 sis_priv->rx_skbuff[entry] = NULL;
1903 struct sis900_private *sis_priv = netdev_priv(net_dev);
1905 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1910 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1911 tx_status = sis_priv->tx_ring[entry].cmdsts;
1922 if (netif_msg_tx_err(sis_priv))
1942 skb = sis_priv->tx_skbuff[entry];
1943 dma_unmap_single(&sis_priv->pci_dev->dev,
1944 sis_priv->tx_ring[entry].bufptr, skb->len,
1947 sis_priv->tx_skbuff[entry] = NULL;
1948 sis_priv->tx_ring[entry].bufptr = 0;
1949 sis_priv->tx_ring[entry].cmdsts = 0;
1952 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1953 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1956 sis_priv->tx_full = 0;
1971 struct sis900_private *sis_priv = netdev_priv(net_dev);
1972 struct pci_dev *pdev = sis_priv->pci_dev;
1973 void __iomem *ioaddr = sis_priv->ioaddr;
1986 del_timer(&sis_priv->timer);
1992 skb = sis_priv->rx_skbuff[i];
1995 sis_priv->rx_ring[i].bufptr,
1998 sis_priv->rx_skbuff[i] = NULL;
2002 skb = sis_priv->tx_skbuff[i];
2005 sis_priv->tx_ring[i].bufptr,
2008 sis_priv->tx_skbuff[i] = NULL;
2028 struct sis900_private *sis_priv = netdev_priv(net_dev);
2032 strscpy(info->bus_info, pci_name(sis_priv->pci_dev),
2038 struct sis900_private *sis_priv = netdev_priv(net_dev);
2039 return sis_priv->msg_enable;
2044 struct sis900_private *sis_priv = netdev_priv(net_dev);
2045 sis_priv->msg_enable = value;
2050 struct sis900_private *sis_priv = netdev_priv(net_dev);
2051 return mii_link_ok(&sis_priv->mii_info);
2057 struct sis900_private *sis_priv = netdev_priv(net_dev);
2058 spin_lock_irq(&sis_priv->lock);
2059 mii_ethtool_get_link_ksettings(&sis_priv->mii_info, cmd);
2060 spin_unlock_irq(&sis_priv->lock);
2067 struct sis900_private *sis_priv = netdev_priv(net_dev);
2069 spin_lock_irq(&sis_priv->lock);
2070 rt = mii_ethtool_set_link_ksettings(&sis_priv->mii_info, cmd);
2071 spin_unlock_irq(&sis_priv->lock);
2077 struct sis900_private *sis_priv = netdev_priv(net_dev);
2078 return mii_nway_restart(&sis_priv->mii_info);
2094 struct sis900_private *sis_priv = netdev_priv(net_dev);
2095 void __iomem *ioaddr = sis_priv->ioaddr;
2099 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2101 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2103 if (netif_msg_wol(sis_priv))
2119 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2121 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2122 if (netif_msg_wol(sis_priv))
2145 struct sis900_private *sis_priv = netdev_priv(dev);
2147 return sis_priv->eeprom_size;
2152 struct sis900_private *sis_priv = netdev_priv(net_dev);
2153 void __iomem *ioaddr = sis_priv->ioaddr;
2159 if (sis_priv->chipset_rev == SIS96x_900_REV) {
2164 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2176 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2187 struct sis900_private *sis_priv = netdev_priv(dev);
2191 eebuf = kmalloc(sis_priv->eeprom_size, GFP_KERNEL);
2196 spin_lock_irq(&sis_priv->lock);
2198 spin_unlock_irq(&sis_priv->lock);
2230 struct sis900_private *sis_priv = netdev_priv(net_dev);
2235 data->phy_id = sis_priv->mii->phy_addr;
2262 struct sis900_private *sis_priv = netdev_priv(dev);
2263 struct mii_phy *mii_phy = sis_priv->mii;
2383 struct sis900_private *sis_priv = netdev_priv(net_dev);
2384 void __iomem *ioaddr = sis_priv->ioaddr;
2390 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2391 (sis_priv->chipset_rev == SIS900B_900_REV))
2418 sis_priv->chipset_rev);
2458 struct sis900_private *sis_priv = netdev_priv(net_dev);
2459 void __iomem *ioaddr = sis_priv->ioaddr;
2473 if (sis_priv->chipset_rev >= SIS635A_900_REV ||
2474 sis_priv->chipset_rev == SIS900B_900_REV)
2490 struct sis900_private *sis_priv = netdev_priv(net_dev);
2494 while (sis_priv->first_mii) {
2495 struct mii_phy *phy = sis_priv->first_mii;
2497 sis_priv->first_mii = phy->next;
2501 dma_free_coherent(&pci_dev->dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2502 sis_priv->rx_ring_dma);
2503 dma_free_coherent(&pci_dev->dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2504 sis_priv->tx_ring_dma);
2505 pci_iounmap(pci_dev, sis_priv->ioaddr);
2512 struct sis900_private *sis_priv = netdev_priv(net_dev);
2513 void __iomem *ioaddr = sis_priv->ioaddr;
2530 struct sis900_private *sis_priv = netdev_priv(net_dev);
2531 void __iomem *ioaddr = sis_priv->ioaddr;
2547 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2554 sis900_check_mode(net_dev, sis_priv->mii);