Lines Matching refs:efx
20 #include "efx.h"
133 #define FALCON_XMAC_STATS_DMA_FLAG(efx) \
134 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
301 static int falcon_reset_hw(struct ef4_nic *efx, enum reset_type method);
302 static void falcon_reconfigure_mac_wrapper(struct ef4_nic *efx);
328 struct ef4_nic *efx = (struct ef4_nic *)data;
331 ef4_reado(efx, ®, FR_AB_GPIO_CTL);
333 ef4_writeo(efx, ®, FR_AB_GPIO_CTL);
338 struct ef4_nic *efx = (struct ef4_nic *)data;
341 ef4_reado(efx, ®, FR_AB_GPIO_CTL);
343 ef4_writeo(efx, ®, FR_AB_GPIO_CTL);
348 struct ef4_nic *efx = (struct ef4_nic *)data;
351 ef4_reado(efx, ®, FR_AB_GPIO_CTL);
357 struct ef4_nic *efx = (struct ef4_nic *)data;
360 ef4_reado(efx, ®, FR_AB_GPIO_CTL);
377 struct ef4_nic *efx = channel->efx;
383 ticks = ef4_usecs_to_ticks(efx, channel->irq_moderation_us);
396 ef4_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
400 static void falcon_deconfigure_mac_wrapper(struct ef4_nic *efx);
402 static void falcon_prepare_flush(struct ef4_nic *efx)
404 falcon_deconfigure_mac_wrapper(efx);
422 static inline void falcon_irq_ack_a1(struct ef4_nic *efx)
427 ef4_writed(efx, ®, FR_AA_INT_ACK_KER);
428 ef4_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
433 struct ef4_nic *efx = dev_id;
434 ef4_oword_t *int_ker = efx->irq_status.addr;
442 netif_vdbg(efx, intr, efx->net_dev,
447 efx->last_irq_cpu = raw_smp_processor_id();
448 netif_vdbg(efx, intr, efx->net_dev,
452 if (!likely(READ_ONCE(efx->irq_soft_enabled)))
458 return ef4_farch_fatal_interrupt(efx);
467 falcon_irq_ack_a1(efx);
470 ef4_schedule_channel_irq(ef4_get_channel(efx, 0));
472 ef4_schedule_channel_irq(ef4_get_channel(efx, 1));
482 static int dummy_rx_push_rss_config(struct ef4_nic *efx, bool user,
485 (void) efx;
491 static int falcon_b0_rx_push_rss_config(struct ef4_nic *efx, bool user,
498 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
499 ef4_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
501 memcpy(efx->rx_indir_table, rx_indir_table,
502 sizeof(efx->rx_indir_table));
503 ef4_farch_rx_push_indir_table(efx);
516 static int falcon_spi_poll(struct ef4_nic *efx)
519 ef4_reado(efx, ®, FR_AB_EE_SPI_HCMD);
524 static int falcon_spi_wait(struct ef4_nic *efx)
534 if (!falcon_spi_poll(efx))
540 if (!falcon_spi_poll(efx))
543 netif_err(efx, hw, efx->net_dev,
552 falcon_spi_cmd(struct ef4_nic *efx, const struct falcon_spi_device *spi,
566 rc = falcon_spi_poll(efx);
573 ef4_writeo(efx, ®, FR_AB_EE_SPI_HADR);
579 ef4_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
592 ef4_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
595 rc = falcon_spi_wait(efx);
601 ef4_reado(efx, ®, FR_AB_EE_SPI_HDATA);
616 falcon_spi_read(struct ef4_nic *efx, const struct falcon_spi_device *spi,
627 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
666 falcon_spi_wait_write(struct ef4_nic *efx, const struct falcon_spi_device *spi)
673 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
680 netif_err(efx, hw, efx->net_dev,
691 falcon_spi_write(struct ef4_nic *efx, const struct falcon_spi_device *spi,
700 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
707 rc = falcon_spi_cmd(efx, spi, command, start + pos,
712 rc = falcon_spi_wait_write(efx, spi);
717 rc = falcon_spi_cmd(efx, spi, command, start + pos,
743 struct ef4_nic *efx = part->common.mtd.priv;
752 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
767 falcon_spi_unlock(struct ef4_nic *efx, const struct falcon_spi_device *spi)
774 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
782 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
785 rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
790 rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
794 rc = falcon_spi_wait_write(efx, spi);
807 struct ef4_nic *efx = part->common.mtd.priv;
819 rc = falcon_spi_unlock(efx, spi);
822 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
825 rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
835 rc = falcon_spi_read(efx, spi, start + pos, block_len,
853 struct ef4_nic *efx = part->mtd.priv;
856 efx->name, part->type_name);
863 struct ef4_nic *efx = mtd->priv;
864 struct falcon_nic_data *nic_data = efx->nic_data;
870 rc = falcon_spi_read(efx, part->spi, part->offset + start,
879 struct ef4_nic *efx = mtd->priv;
880 struct falcon_nic_data *nic_data = efx->nic_data;
895 struct ef4_nic *efx = mtd->priv;
896 struct falcon_nic_data *nic_data = efx->nic_data;
902 rc = falcon_spi_write(efx, part->spi, part->offset + start,
911 struct ef4_nic *efx = mtd->priv;
912 struct falcon_nic_data *nic_data = efx->nic_data;
921 static int falcon_mtd_probe(struct ef4_nic *efx)
923 struct falcon_nic_data *nic_data = efx->nic_data;
965 rc = ef4_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
981 static void falcon_setup_xaui(struct ef4_nic *efx)
987 if (efx->phy_type == PHY_TYPE_NONE)
990 ef4_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
999 ef4_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
1010 ef4_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
1013 int falcon_reset_xaui(struct ef4_nic *efx)
1015 struct falcon_nic_data *nic_data = efx->nic_data;
1024 ef4_writeo(efx, ®, FR_AB_XX_PWR_RST);
1028 ef4_reado(efx, ®, FR_AB_XX_PWR_RST);
1031 falcon_setup_xaui(efx);
1036 netif_err(efx, hw, efx->net_dev,
1041 static void falcon_ack_status_intr(struct ef4_nic *efx)
1043 struct falcon_nic_data *nic_data = efx->nic_data;
1046 if ((ef4_nic_rev(efx) != EF4_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1050 if (!efx->link_state.up)
1058 ef4_reado(efx, ®, FR_AB_XM_MGT_INT_MSK);
1061 static bool falcon_xgxs_link_ok(struct ef4_nic *efx)
1068 ef4_reado(efx, ®, FR_AB_XX_CORE_STAT);
1079 ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT);
1084 static bool falcon_xmac_link_ok(struct ef4_nic *efx)
1092 return (efx->loopback_mode == LOOPBACK_XGMII ||
1093 falcon_xgxs_link_ok(efx)) &&
1094 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1095 LOOPBACK_INTERNAL(efx) ||
1096 ef4_mdio_phyxgxs_lane_sync(efx));
1099 static void falcon_reconfigure_xmac_core(struct ef4_nic *efx)
1103 bool rx_fc = !!(efx->link_state.fc & EF4_FC_RX);
1104 bool tx_fc = !!(efx->link_state.fc & EF4_FC_TX);
1111 ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1121 ef4_writeo(efx, ®, FR_AB_XM_TX_CFG);
1128 FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1130 ef4_writeo(efx, ®, FR_AB_XM_RX_CFG);
1133 max_frame_len = EF4_MAX_FRAME_LEN(efx->net_dev->mtu);
1135 ef4_writeo(efx, ®, FR_AB_XM_RX_PARAM);
1139 ef4_writeo(efx, ®, FR_AB_XM_TX_PARAM);
1144 ef4_writeo(efx, ®, FR_AB_XM_FC);
1147 memcpy(®, &efx->net_dev->dev_addr[0], 4);
1148 ef4_writeo(efx, ®, FR_AB_XM_ADR_LO);
1149 memcpy(®, &efx->net_dev->dev_addr[4], 2);
1150 ef4_writeo(efx, ®, FR_AB_XM_ADR_HI);
1153 static void falcon_reconfigure_xgxs_core(struct ef4_nic *efx)
1156 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1157 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1158 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1163 ef4_reado(efx, ®, FR_AB_XX_CORE_STAT);
1167 ef4_reado(efx, ®, FR_AB_XX_SD_CTL);
1174 falcon_reset_xaui(efx);
1176 ef4_reado(efx, ®, FR_AB_XX_CORE_STAT);
1182 ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT);
1184 ef4_reado(efx, ®, FR_AB_XX_SD_CTL);
1189 ef4_writeo(efx, ®, FR_AB_XX_SD_CTL);
1194 static bool falcon_xmac_link_ok_retry(struct ef4_nic *efx, int tries)
1196 bool mac_up = falcon_xmac_link_ok(efx);
1198 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1199 ef4_phy_mode_disabled(efx->phy_mode))
1203 falcon_stop_nic_stats(efx);
1206 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1207 falcon_reset_xaui(efx);
1210 mac_up = falcon_xmac_link_ok(efx);
1214 falcon_start_nic_stats(efx);
1219 static bool falcon_xmac_check_fault(struct ef4_nic *efx)
1221 return !falcon_xmac_link_ok_retry(efx, 5);
1224 static int falcon_reconfigure_xmac(struct ef4_nic *efx)
1226 struct falcon_nic_data *nic_data = efx->nic_data;
1228 ef4_farch_filter_sync_rx_mode(efx);
1230 falcon_reconfigure_xgxs_core(efx);
1231 falcon_reconfigure_xmac_core(efx);
1233 falcon_reconfigure_mac_wrapper(efx);
1235 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1236 falcon_ack_status_intr(efx);
1241 static void falcon_poll_xmac(struct ef4_nic *efx)
1243 struct falcon_nic_data *nic_data = efx->nic_data;
1246 if (!efx->link_state.up || !nic_data->xmac_poll_required)
1249 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1250 falcon_ack_status_intr(efx);
1260 static void falcon_push_multicast_hash(struct ef4_nic *efx)
1262 union ef4_multicast_hash *mc_hash = &efx->multicast_hash;
1264 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1266 ef4_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1267 ef4_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1270 static void falcon_reset_macs(struct ef4_nic *efx)
1272 struct falcon_nic_data *nic_data = efx->nic_data;
1276 if (ef4_nic_rev(efx) < EF4_REV_FALCON_B0) {
1281 ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1284 ef4_reado(efx, ®, FR_AB_XM_GLB_CFG);
1291 netif_err(efx, hw, efx->net_dev,
1298 ef4_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1300 ef4_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1302 ef4_reado(efx, ®, FR_AB_GLB_CTL);
1306 ef4_writeo(efx, ®, FR_AB_GLB_CTL);
1310 ef4_reado(efx, ®, FR_AB_GLB_CTL);
1314 netif_dbg(efx, hw, efx->net_dev,
1320 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1329 ef4_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1331 falcon_setup_xaui(efx);
1334 static void falcon_drain_tx_fifo(struct ef4_nic *efx)
1338 if ((ef4_nic_rev(efx) < EF4_REV_FALCON_B0) ||
1339 (efx->loopback_mode != LOOPBACK_NONE))
1342 ef4_reado(efx, ®, FR_AB_MAC_CTRL);
1347 falcon_reset_macs(efx);
1350 static void falcon_deconfigure_mac_wrapper(struct ef4_nic *efx)
1354 if (ef4_nic_rev(efx) < EF4_REV_FALCON_B0)
1358 ef4_reado(efx, ®, FR_AZ_RX_CFG);
1360 ef4_writeo(efx, ®, FR_AZ_RX_CFG);
1363 falcon_drain_tx_fifo(efx);
1366 static void falcon_reconfigure_mac_wrapper(struct ef4_nic *efx)
1368 struct ef4_link_state *link_state = &efx->link_state;
1372 isolate = !!READ_ONCE(efx->reset_pending);
1388 FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1393 if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) {
1398 ef4_writeo(efx, ®, FR_AB_MAC_CTRL);
1401 falcon_push_multicast_hash(efx);
1403 ef4_reado(efx, ®, FR_AZ_RX_CFG);
1408 if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0)
1410 ef4_writeo(efx, ®, FR_AZ_RX_CFG);
1413 static void falcon_stats_request(struct ef4_nic *efx)
1415 struct falcon_nic_data *nic_data = efx->nic_data;
1421 FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1429 efx->stats_buffer.dma_addr);
1430 ef4_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
1435 static void falcon_stats_complete(struct ef4_nic *efx)
1437 struct falcon_nic_data *nic_data = efx->nic_data;
1443 if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1447 efx->stats_buffer.addr, true);
1449 netif_err(efx, hw, efx->net_dev,
1458 struct ef4_nic *efx = nic_data->efx;
1460 spin_lock(&efx->stats_lock);
1462 falcon_stats_complete(efx);
1464 falcon_stats_request(efx);
1466 spin_unlock(&efx->stats_lock);
1469 static bool falcon_loopback_link_poll(struct ef4_nic *efx)
1471 struct ef4_link_state old_state = efx->link_state;
1473 WARN_ON(!mutex_is_locked(&efx->mac_lock));
1474 WARN_ON(!LOOPBACK_INTERNAL(efx));
1476 efx->link_state.fd = true;
1477 efx->link_state.fc = efx->wanted_fc;
1478 efx->link_state.up = true;
1479 efx->link_state.speed = 10000;
1481 return !ef4_link_state_equal(&efx->link_state, &old_state);
1484 static int falcon_reconfigure_port(struct ef4_nic *efx)
1488 WARN_ON(ef4_nic_rev(efx) > EF4_REV_FALCON_B0);
1494 if (LOOPBACK_INTERNAL(efx))
1495 falcon_loopback_link_poll(efx);
1497 efx->phy_op->poll(efx);
1499 falcon_stop_nic_stats(efx);
1500 falcon_deconfigure_mac_wrapper(efx);
1502 falcon_reset_macs(efx);
1504 efx->phy_op->reconfigure(efx);
1505 rc = falcon_reconfigure_xmac(efx);
1508 falcon_start_nic_stats(efx);
1510 /* Synchronise efx->link_state with the kernel */
1511 ef4_link_status_changed(efx);
1523 static void falcon_a1_prepare_enable_fc_tx(struct ef4_nic *efx)
1526 ef4_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1529 static void falcon_b0_prepare_enable_fc_tx(struct ef4_nic *efx)
1532 falcon_stop_nic_stats(efx);
1533 falcon_drain_tx_fifo(efx);
1534 falcon_reconfigure_xmac(efx);
1535 falcon_start_nic_stats(efx);
1546 static int falcon_gmii_wait(struct ef4_nic *efx)
1553 ef4_reado(efx, &md_stat, FR_AB_MD_STAT);
1557 netif_err(efx, hw, efx->net_dev,
1567 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1575 struct ef4_nic *efx = netdev_priv(net_dev);
1576 struct falcon_nic_data *nic_data = efx->nic_data;
1580 netif_vdbg(efx, hw, efx->net_dev,
1587 rc = falcon_gmii_wait(efx);
1593 ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR);
1597 ef4_writeo(efx, ®, FR_AB_MD_ID);
1601 ef4_writeo(efx, ®, FR_AB_MD_TXD);
1606 ef4_writeo(efx, ®, FR_AB_MD_CS);
1609 rc = falcon_gmii_wait(efx);
1615 ef4_writeo(efx, ®, FR_AB_MD_CS);
1628 struct ef4_nic *efx = netdev_priv(net_dev);
1629 struct falcon_nic_data *nic_data = efx->nic_data;
1636 rc = falcon_gmii_wait(efx);
1641 ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR);
1645 ef4_writeo(efx, ®, FR_AB_MD_ID);
1649 ef4_writeo(efx, ®, FR_AB_MD_CS);
1652 rc = falcon_gmii_wait(efx);
1654 ef4_reado(efx, ®, FR_AB_MD_RXD);
1656 netif_vdbg(efx, hw, efx->net_dev,
1664 ef4_writeo(efx, ®, FR_AB_MD_CS);
1666 netif_dbg(efx, hw, efx->net_dev,
1677 static int falcon_probe_port(struct ef4_nic *efx)
1679 struct falcon_nic_data *nic_data = efx->nic_data;
1682 switch (efx->phy_type) {
1684 efx->phy_op = &falcon_sfx7101_phy_ops;
1688 efx->phy_op = &falcon_qt202x_phy_ops;
1691 efx->phy_op = &falcon_txc_phy_ops;
1694 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1695 efx->phy_type);
1701 efx->mdio.mdio_read = falcon_mdio_read;
1702 efx->mdio.mdio_write = falcon_mdio_write;
1703 rc = efx->phy_op->probe(efx);
1708 efx->link_state.speed = 10000;
1709 efx->link_state.fd = true;
1712 if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0)
1713 efx->wanted_fc = EF4_FC_RX | EF4_FC_TX;
1715 efx->wanted_fc = EF4_FC_RX;
1716 if (efx->mdio.mmds & MDIO_DEVS_AN)
1717 efx->wanted_fc |= EF4_FC_AUTO;
1720 rc = ef4_nic_alloc_buffer(efx, &efx->stats_buffer,
1724 netif_dbg(efx, probe, efx->net_dev,
1726 (u64)efx->stats_buffer.dma_addr,
1727 efx->stats_buffer.addr,
1728 (u64)virt_to_phys(efx->stats_buffer.addr));
1733 static void falcon_remove_port(struct ef4_nic *efx)
1735 efx->phy_op->remove(efx);
1736 ef4_nic_free_buffer(efx, &efx->stats_buffer);
1743 struct ef4_nic *efx = channel->efx;
1744 struct falcon_nic_data *nic_data = efx->nic_data;
1752 if ((ef4_nic_rev(efx) == EF4_REV_FALCON_B0) &&
1758 if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1 ?
1761 netif_err(efx, rx_err, efx->net_dev,
1765 atomic_inc(&efx->rx_reset);
1766 ef4_schedule_reset(efx, EF4_WORKAROUND_6555(efx) ?
1781 falcon_read_nvram(struct ef4_nic *efx, struct falcon_nvconfig *nvconfig_out)
1783 struct falcon_nic_data *nic_data = efx->nic_data;
1804 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1807 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1819 netif_err(efx, hw, efx->net_dev,
1824 netif_err(efx, hw, efx->net_dev,
1838 netif_err(efx, hw, efx->net_dev,
1852 static int falcon_test_nvram(struct ef4_nic *efx)
1854 return falcon_read_nvram(efx, NULL);
1897 falcon_b0_test_chip(struct ef4_nic *efx, struct ef4_self_tests *tests)
1902 mutex_lock(&efx->mac_lock);
1903 if (efx->loopback_modes) {
1906 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1907 efx->loopback_mode = LOOPBACK_XGMII;
1909 efx->loopback_mode = __ffs(efx->loopback_modes);
1911 __ef4_reconfigure_port(efx);
1912 mutex_unlock(&efx->mac_lock);
1914 ef4_reset_down(efx, reset_method);
1917 ef4_farch_test_registers(efx, falcon_b0_register_tests,
1921 rc = falcon_reset_hw(efx, reset_method);
1922 rc2 = ef4_reset_up(efx, reset_method, rc == 0);
1977 static int __falcon_reset_hw(struct ef4_nic *efx, enum reset_type method)
1979 struct falcon_nic_data *nic_data = efx->nic_data;
1983 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1988 rc = pci_save_state(efx->pci_dev);
1990 netif_err(efx, drv, efx->net_dev,
1995 if (ef4_nic_is_dual_func(efx)) {
1998 netif_err(efx, drv, efx->net_dev,
2024 ef4_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2026 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
2031 if (ef4_nic_is_dual_func(efx))
2033 pci_restore_state(efx->pci_dev);
2034 netif_dbg(efx, drv, efx->net_dev,
2039 ef4_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2042 netif_err(efx, hw, efx->net_dev,
2046 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2052 pci_restore_state(efx->pci_dev);
2058 static int falcon_reset_hw(struct ef4_nic *efx, enum reset_type method)
2060 struct falcon_nic_data *nic_data = efx->nic_data;
2064 rc = __falcon_reset_hw(efx, method);
2070 static void falcon_monitor(struct ef4_nic *efx)
2075 BUG_ON(!mutex_is_locked(&efx->mac_lock));
2077 rc = falcon_board(efx)->type->monitor(efx);
2079 netif_err(efx, hw, efx->net_dev,
2082 efx->phy_mode |= PHY_MODE_LOW_POWER;
2083 rc = __ef4_reconfigure_port(efx);
2087 if (LOOPBACK_INTERNAL(efx))
2088 link_changed = falcon_loopback_link_poll(efx);
2090 link_changed = efx->phy_op->poll(efx);
2093 falcon_stop_nic_stats(efx);
2094 falcon_deconfigure_mac_wrapper(efx);
2096 falcon_reset_macs(efx);
2097 rc = falcon_reconfigure_xmac(efx);
2100 falcon_start_nic_stats(efx);
2102 ef4_link_status_changed(efx);
2105 falcon_poll_xmac(efx);
2111 static int falcon_reset_sram(struct ef4_nic *efx)
2117 ef4_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2120 ef4_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2126 ef4_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2131 netif_dbg(efx, hw, efx->net_dev,
2138 ef4_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2140 netif_dbg(efx, hw, efx->net_dev,
2147 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2151 static void falcon_spi_device_init(struct ef4_nic *efx,
2177 static int falcon_probe_nvconfig(struct ef4_nic *efx)
2179 struct falcon_nic_data *nic_data = efx->nic_data;
2187 rc = falcon_read_nvram(efx, nvconfig);
2191 efx->phy_type = nvconfig->board_v2.port0_phy_type;
2192 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2196 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2200 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2206 ether_addr_copy(efx->net_dev->perm_addr, nvconfig->mac_address[0]);
2208 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2209 efx->phy_type, efx->mdio.prtad);
2211 rc = falcon_probe_board(efx,
2218 static int falcon_dimension_resources(struct ef4_nic *efx)
2220 efx->rx_dc_base = 0x20000;
2221 efx->tx_dc_base = 0x26000;
2226 static void falcon_probe_spi_devices(struct ef4_nic *efx)
2228 struct falcon_nic_data *nic_data = efx->nic_data;
2232 ef4_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2233 ef4_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2234 ef4_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2239 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2246 netif_dbg(efx, probe, efx->net_dev,
2254 ef4_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2260 falcon_spi_device_init(efx, &nic_data->spi_flash,
2264 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2269 static unsigned int falcon_a1_mem_map_size(struct ef4_nic *efx)
2274 static unsigned int falcon_b0_mem_map_size(struct ef4_nic *efx)
2283 static int falcon_probe_nic(struct ef4_nic *efx)
2289 efx->primary = efx; /* only one usable function per controller */
2295 efx->nic_data = nic_data;
2296 nic_data->efx = efx;
2300 if (ef4_farch_fpga_ver(efx) != 0) {
2301 netif_err(efx, probe, efx->net_dev,
2306 if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1) {
2309 u8 pci_rev = efx->pci_dev->revision;
2312 netif_err(efx, probe, efx->net_dev,
2316 ef4_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2318 netif_err(efx, probe, efx->net_dev,
2323 netif_err(efx, probe, efx->net_dev,
2328 dev = pci_dev_get(efx->pci_dev);
2332 if (dev->bus == efx->pci_dev->bus &&
2333 dev->devfn == efx->pci_dev->devfn + 1) {
2339 netif_err(efx, probe, efx->net_dev,
2347 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2349 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2354 rc = ef4_nic_alloc_buffer(efx, &efx->irq_status, sizeof(ef4_oword_t),
2358 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2360 netif_dbg(efx, probe, efx->net_dev,
2362 (u64)efx->irq_status.dma_addr,
2363 efx->irq_status.addr,
2364 (u64)virt_to_phys(efx->irq_status.addr));
2366 falcon_probe_spi_devices(efx);
2369 rc = falcon_probe_nvconfig(efx);
2372 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2376 efx->max_channels = (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1 ? 4 :
2378 efx->max_tx_channels = efx->max_channels;
2379 efx->timer_quantum_ns = 4968; /* 621 cycles */
2380 efx->timer_max_ns = efx->type->timer_period_max *
2381 efx->timer_quantum_ns;
2384 board = falcon_board(efx);
2387 board->i2c_data.data = efx;
2389 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2396 rc = falcon_board(efx)->type->init(efx);
2398 netif_err(efx, probe, efx->net_dev,
2412 ef4_nic_free_buffer(efx, &efx->irq_status);
2421 kfree(efx->nic_data);
2425 static void falcon_init_rx_cfg(struct ef4_nic *efx)
2432 ef4_reado(efx, ®, FR_AZ_RX_CFG);
2433 if (ef4_nic_rev(efx) <= EF4_REV_FALCON_A1) {
2469 ef4_writeo(efx, ®, FR_AZ_RX_CFG);
2476 static int falcon_init_nic(struct ef4_nic *efx)
2482 ef4_reado(efx, &temp, FR_AB_NIC_STAT);
2484 ef4_writeo(efx, &temp, FR_AB_NIC_STAT);
2486 rc = falcon_reset_sram(efx);
2493 if (EF4_WORKAROUND_5129(efx)) {
2494 ef4_reado(efx, &temp, FR_AZ_CSR_SPARE);
2496 ef4_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2499 if (EF4_WORKAROUND_7244(efx)) {
2500 ef4_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2505 ef4_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2512 ef4_reado(efx, &temp, FR_AA_RX_SELF_RST);
2515 if (EF4_WORKAROUND_5583(efx))
2517 ef4_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2522 ef4_reado(efx, &temp, FR_AZ_TX_CFG);
2524 ef4_writeo(efx, &temp, FR_AZ_TX_CFG);
2526 falcon_init_rx_cfg(efx);
2528 if (ef4_nic_rev(efx) >= EF4_REV_FALCON_B0) {
2529 falcon_b0_rx_push_rss_config(efx, false, efx->rx_indir_table);
2533 ef4_writeo(efx, &temp, FR_BZ_DP_CTRL);
2536 ef4_farch_init_common(efx);
2541 static void falcon_remove_nic(struct ef4_nic *efx)
2543 struct falcon_nic_data *nic_data = efx->nic_data;
2544 struct falcon_board *board = falcon_board(efx);
2546 board->type->fini(efx);
2552 ef4_nic_free_buffer(efx, &efx->irq_status);
2554 __falcon_reset_hw(efx, RESET_TYPE_ALL);
2563 kfree(efx->nic_data);
2564 efx->nic_data = NULL;
2567 static size_t falcon_describe_nic_stats(struct ef4_nic *efx, u8 *names)
2573 static size_t falcon_update_nic_stats(struct ef4_nic *efx, u64 *full_stats,
2576 struct falcon_nic_data *nic_data = efx->nic_data;
2581 ef4_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2586 FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2592 stats, efx->stats_buffer.addr, true);
2600 ef4_update_sw_stats(efx, stats);
2631 void falcon_start_nic_stats(struct ef4_nic *efx)
2633 struct falcon_nic_data *nic_data = efx->nic_data;
2635 spin_lock_bh(&efx->stats_lock);
2637 falcon_stats_request(efx);
2638 spin_unlock_bh(&efx->stats_lock);
2644 static void falcon_pull_nic_stats(struct ef4_nic *efx)
2649 void falcon_stop_nic_stats(struct ef4_nic *efx)
2651 struct falcon_nic_data *nic_data = efx->nic_data;
2656 spin_lock_bh(&efx->stats_lock);
2658 spin_unlock_bh(&efx->stats_lock);
2665 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2670 spin_lock_bh(&efx->stats_lock);
2671 falcon_stats_complete(efx);
2672 spin_unlock_bh(&efx->stats_lock);
2675 static void falcon_set_id_led(struct ef4_nic *efx, enum ef4_led_mode mode)
2677 falcon_board(efx)->type->set_id_led(efx, mode);
2687 static void falcon_get_wol(struct ef4_nic *efx, struct ethtool_wolinfo *wol)
2694 static int falcon_set_wol(struct ef4_nic *efx, u32 type)
2703 * Revision-dependent attributes used by efx.c and nic.c