Lines Matching defs:offset
26 * that the capability is vendor specified. i.e. offset from value returned by
38 u64 offset;
41 static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
44 /* Number of bytes to offset when reading bit position x with dword accessors. */
69 u64 offset = ef100_pci_get_bar_bits(efx, entry_location, EF100_FUNC_CTL_WIN_OFF) <<
74 "Found EF100 function control window bar=%d offset=0x%llx\n",
75 bar, offset);
92 result->offset = offset;
112 u64 offset;
120 offset = EFX_OWORD_FIELD64(entry, ESF_GZ_CFGBAR_CONT_CAP_OFFSET) <<
136 if (ef100_pci_does_bar_overflow(efx, bar, offset)) {
138 "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
139 bar, offset);
154 rc = ef100_pci_walk_xilinx_table(efx, offset, result);
179 static int ef100_pci_walk_xilinx_table(struct efx_nic *efx, u64 offset,
182 u64 current_entry = offset;
286 u64 offset = 0;
314 /* Get optional extension to 64bit offset. */
325 offset = (((u64)offset_lo) << ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT) |
328 if (offset > pci_resource_len(efx->pci_dev, bar) - sizeof(u32) * 2) {
330 "Xilinx table will overrun BAR[%d] offset=0x%llx\n",
331 bar, offset);
345 rc = ef100_pci_walk_xilinx_table(efx, offset, result);
484 fcw.offset = 0;
488 if (fcw.offset > pci_resource_len(efx->pci_dev, fcw.bar) - ESE_GZ_FCW_LEN) {
501 efx->reg_base = fcw.offset;