Lines Matching refs:addr
28 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected)
32 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected,
36 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set)
38 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg);
44 iowrite32(RRC_RR, priv->addr + RRC);
45 iowrite32(RRC_RR_CLR, priv->addr + RRC);
50 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC);
55 iowrite32(RCDC_RCD, priv->addr + RCDC);
85 val = ioread32(priv->addr + CABPIRM);
89 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM);
91 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR);
96 iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0);
105 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i));
115 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i));
116 iowrite32(0, priv->addr + FWPBFC(i));
121 priv->addr + FWPBFCSDC(GWCA_INDEX, i));
122 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i));
126 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index));
127 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index));
128 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index));
129 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index));
138 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index))
139 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1);
141 iowrite32(mode, priv->addr + GWMC);
143 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode);
146 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0);
153 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM);
155 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR);
160 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM);
162 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR);
183 dis[i] = ioread32(priv->addr + GWDIS(i));
184 dis[i] &= ioread32(priv->addr + GWDIE(i));
192 iowrite32(BIT(index % 32), priv->addr + offs);
199 iowrite32(BIT(index % 32), priv->addr + offs);
338 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr)
340 desc->dptrl = cpu_to_le32(lower_32_bits(addr));
341 desc->dptrh = upper_32_bits(addr) & 0xff;
383 priv->addr + GWDCC_OFFS(gq->index));
482 priv->addr + GWDCC_OFFS(gq->index));
645 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC);
646 iowrite32(0, priv->addr + GWTTFC);
647 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1);
648 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0);
649 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10);
650 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00);
651 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0);
653 iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0);
958 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) {
959 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS);
989 iowrite32(mode, etha->addr + EAMC);
991 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode);
1001 u32 mrmac0 = ioread32(etha->addr + MRMAC0);
1002 u32 mrmac1 = ioread32(etha->addr + MRMAC1);
1015 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
1017 etha->addr + MRMAC1);
1022 iowrite32(MLVC_PLV, etha->addr + MLVC);
1024 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0);
1047 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);
1052 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
1054 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45);
1068 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC);
1093 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
1096 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1098 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1102 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1105 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1107 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1111 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
1113 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1116 etha->addr + MPSM);
1118 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);
1124 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad,
1129 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0);
1132 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad,
1137 return rswitch_etha_set_access(etha, false, addr, devad, regad, val);
1462 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE);
1479 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID);
1552 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32));
1699 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE;
1700 etha->coma_addr = priv->addr;
1732 rdev->addr = priv->addr;
1734 ndev->base_addr = (unsigned long)rdev->addr;
1928 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1929 if (IS_ERR(priv->addr))
1930 return PTR_ERR(priv->addr);
1932 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4;