Lines Matching defs:etha

436 			desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index));
981 static int rswitch_etha_change_mode(struct rswitch_etha *etha,
986 	if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index))
987 		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1);
989 	iowrite32(mode, etha->addr + EAMC);
991 	ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode);
994 		rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0);
999 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha)
1001 	u32 mrmac0 = ioread32(etha->addr + MRMAC0);
1002 	u32 mrmac1 = ioread32(etha->addr + MRMAC1);
1003 	u8 *mac = &etha->mac_addr[0];
1013 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac)
1015 	iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
1017 		  etha->addr + MRMAC1);
1020 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)
1022 	iowrite32(MLVC_PLV, etha->addr + MLVC);
1024 	return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0);
1027 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
1031 	rswitch_etha_write_mac_address(etha, mac);
1033 	switch (etha->speed) {
1047 	iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);
1050 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
1052 	rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
1053 		       MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06));
1054 	rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45);
1057 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
1061 	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1064 	err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG);
1068 	iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC);
1069 	rswitch_rmac_setting(etha, mac);
1070 	rswitch_etha_enable_mii(etha);
1072 	err = rswitch_etha_wait_link_verification(etha);
1076 	err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE);
1080 	return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION);
1083 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read,
1093 	writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
1096 	iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1098 	ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1102 	rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);
1105 		writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);
1107 		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1111 		ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
1113 		rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);
1116 			  etha->addr + MPSM);
1118 		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);
1127 	struct rswitch_etha *etha = bus->priv;
1129 	return rswitch_etha_set_access(etha, true, addr, devad, regad, 0);
1135 	struct rswitch_etha *etha = bus->priv;
1137 	return rswitch_etha_set_access(etha, false, addr, devad, regad, val);
1158 		if (index == rdev->etha->index) {
1179 	err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface);
1185 		rdev->etha->speed = max_speed;
1190 	switch (rdev->etha->phy_interface) {
1192 		rdev->etha->speed = SPEED_100;
1195 		rdev->etha->speed = SPEED_1000;
1198 		rdev->etha->speed = SPEED_2500;
1218 	sprintf(mii_bus->id, "etha%d", rdev->etha->index);
1219 	mii_bus->priv = rdev->etha;
1231 	rdev->etha->mii = mii_bus;
1241 	if (rdev->etha->mii) {
1242 		mdiobus_unregister(rdev->etha->mii);
1243 		mdiobus_free(rdev->etha->mii);
1244 		rdev->etha->mii = NULL;
1253 	if (phydev->link != rdev->etha->link) {
1260 		rdev->etha->link = phydev->link;
1263 		    phydev->speed != rdev->etha->speed) {
1264 			rdev->etha->speed = phydev->speed;
1266 			rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);
1267 			phy_set_speed(rdev->serdes, rdev->etha->speed);
1278 	switch (rdev->etha->speed) {
1295 	phy_set_max_speed(phydev, rdev->etha->speed);
1317 	__set_bit(rdev->etha->phy_interface, phydev->host_interfaces);
1320 				rdev->etha->phy_interface);
1351 			       rdev->etha->phy_interface);
1355 	return phy_set_speed(rdev->serdes, rdev->etha->speed);
1362 	if (!rdev->etha->operated) {
1363 		err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr);
1367 			rdev->etha->operated = true;
1525 	desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) |
1695 	struct rswitch_etha *etha = &priv->etha[index];
1697 	memset(etha, 0, sizeof(*etha));
1698 	etha->index = index;
1699 	etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE;
1700 	etha->coma_addr = priv->addr;
1706 	etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1;
1731 	rdev->etha = &priv->etha[index];
1746 		if (is_valid_ether_addr(rdev->etha->mac_addr))
1747 			eth_hw_addr_set(ndev, rdev->etha->mac_addr);
1756 	if (rdev->priv->gwca.speed < rdev->etha->speed)
1757 		rdev->priv->gwca.speed = rdev->etha->speed;
1800 		rswitch_etha_read_mac_address(&priv->etha[i]);