Lines Matching refs:tp
80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
642 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
669 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
671 return &tp->pci_dev->dev;
674 static void rtl_lock_config_regs(struct rtl8169_private *tp)
678 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
679 if (!--tp->cfg9346_usage_count)
680 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
681 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
684 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
688 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
689 if (!tp->cfg9346_usage_count++)
690 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
691 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
694 static void rtl_pci_commit(struct rtl8169_private *tp)
697 RTL_R8(tp, ChipCmd);
700 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
705 raw_spin_lock_irqsave(&tp->config25_lock, flags);
706 val = RTL_R8(tp, Config2);
707 RTL_W8(tp, Config2, (val & ~clear) | set);
708 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
711 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
716 raw_spin_lock_irqsave(&tp->config25_lock, flags);
717 val = RTL_R8(tp, Config5);
718 RTL_W8(tp, Config5, (val & ~clear) | set);
719 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
722 static bool rtl_is_8125(struct rtl8169_private *tp)
724 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
727 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
729 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
730 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
731 tp->mac_version <= RTL_GIGA_MAC_VER_53;
734 static bool rtl_supports_eee(struct rtl8169_private *tp)
736 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
737 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
738 tp->mac_version != RTL_GIGA_MAC_VER_39;
741 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
746 mac[i] = RTL_R8(tp, reg + i);
754 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
760 if (c->check(tp) == high)
766 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
771 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
775 return rtl_loop_wait(tp, c, d, n, true);
778 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
782 return rtl_loop_wait(tp, c, d, n, false);
793 static bool name ## _check(struct rtl8169_private *tp)
795 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
799 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
800 tp->mac_version == RTL_GIGA_MAC_VER_53))
806 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
809 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
817 RTL_W32(tp, ERIDR, val);
818 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
819 RTL_W32(tp, ERIAR, cmd);
821 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
824 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
827 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
830 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
834 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
835 RTL_W32(tp, ERIAR, cmd);
837 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
838 RTL_R32(tp, ERIDR) : ~0;
841 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
843 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
846 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
848 u32 val = rtl_eri_read(tp, addr);
850 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
853 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
855 rtl_w0w1_eri(tp, addr, p, 0);
858 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
860 rtl_w0w1_eri(tp, addr, 0, m);
870 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
873 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
878 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
880 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
883 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
888 RTL_W32(tp, GPHY_OCP, reg << 15);
890 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
891 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
894 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
899 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
902 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
906 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
907 __r8168_mac_ocp_write(tp, reg, data);
908 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
911 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
916 RTL_W32(tp, OCPDR, reg << 15);
918 return RTL_R32(tp, OCPDR);
921 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
926 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
927 val = __r8168_mac_ocp_read(tp, reg);
928 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
933 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
939 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
940 data = __r8168_mac_ocp_read(tp, reg);
941 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
942 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
948 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
950 switch (tp->mac_version) {
953 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
955 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
962 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
965 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
969 if (tp->ocp_base != OCP_STD_PHY_BASE)
972 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
973 rtl8168g_phy_suspend_quirk(tp, value);
975 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
978 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
981 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
983 if (tp->ocp_base != OCP_STD_PHY_BASE)
986 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
989 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
992 tp->ocp_base = value << 4;
996 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
999 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1001 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1006 return RTL_R32(tp, PHYAR) & 0x80000000;
1009 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1011 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1013 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1021 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1025 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1027 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1028 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1041 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1046 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1048 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1051 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1053 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1056 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1058 r8168dp_2_mdio_start(tp);
1060 r8169_mdio_write(tp, reg, value);
1062 r8168dp_2_mdio_stop(tp);
1065 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1073 r8168dp_2_mdio_start(tp);
1075 value = r8169_mdio_read(tp, reg);
1077 r8168dp_2_mdio_stop(tp);
1082 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1084 switch (tp->mac_version) {
1087 r8168dp_2_mdio_write(tp, location, val);
1090 r8168g_mdio_write(tp, location, val);
1093 r8169_mdio_write(tp, location, val);
1098 static int rtl_readphy(struct rtl8169_private *tp, int location)
1100 switch (tp->mac_version) {
1103 return r8168dp_2_mdio_read(tp, location);
1105 return r8168g_mdio_read(tp, location);
1107 return r8169_mdio_read(tp, location);
1113 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1116 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1118 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1121 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1126 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1128 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1130 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1131 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1134 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1136 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1137 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1138 RTL_R32(tp, OCPDR) : ~0;
1141 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1143 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1146 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1149 RTL_W32(tp, OCPDR, data);
1150 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1151 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1154 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1157 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1161 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1163 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1165 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1172 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1174 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1181 reg = rtl8168_get_ocp_reg(tp);
1183 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1188 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1193 return RTL_R8(tp, IBISR0) & 0x20;
1196 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1198 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1199 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1200 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1201 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1204 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1206 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1207 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1210 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1213 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1214 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1217 static void rtl8168_driver_start(struct rtl8169_private *tp)
1219 if (tp->dash_type == RTL_DASH_DP)
1220 rtl8168dp_driver_start(tp);
1222 rtl8168ep_driver_start(tp);
1225 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1227 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1228 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1231 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1233 rtl8168ep_stop_cmac(tp);
1234 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1235 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1236 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1239 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1241 if (tp->dash_type == RTL_DASH_DP)
1242 rtl8168dp_driver_stop(tp);
1244 rtl8168ep_driver_stop(tp);
1247 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1249 u16 reg = rtl8168_get_ocp_reg(tp);
1251 return r8168dp_ocp_read(tp, reg) & BIT(15);
1254 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1256 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1259 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1261 switch (tp->dash_type) {
1263 return r8168dp_check_dash(tp);
1265 return r8168ep_check_dash(tp);
1271 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1273 switch (tp->mac_version) {
1284 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1286 switch (tp->mac_version) {
1292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1294 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1301 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1303 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1304 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1309 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1312 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1314 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1316 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1320 static u32 rtl_get_events(struct rtl8169_private *tp)
1322 if (rtl_is_8125(tp))
1323 return RTL_R32(tp, IntrStatus_8125);
1325 return RTL_R16(tp, IntrStatus);
1328 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1330 if (rtl_is_8125(tp))
1331 RTL_W32(tp, IntrStatus_8125, bits);
1333 RTL_W16(tp, IntrStatus, bits);
1336 static void rtl_irq_disable(struct rtl8169_private *tp)
1338 if (rtl_is_8125(tp))
1339 RTL_W32(tp, IntrMask_8125, 0);
1341 RTL_W16(tp, IntrMask, 0);
1344 static void rtl_irq_enable(struct rtl8169_private *tp)
1346 if (rtl_is_8125(tp))
1347 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1349 RTL_W16(tp, IntrMask, tp->irq_mask);
1352 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1354 rtl_irq_disable(tp);
1355 rtl_ack_events(tp, 0xffffffff);
1356 rtl_pci_commit(tp);
1359 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1361 struct phy_device *phydev = tp->phydev;
1363 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1364 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1366 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1367 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1369 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1370 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1373 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1375 rtl_reset_packet_filter(tp);
1376 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1377 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1379 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1380 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1382 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1383 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1385 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1387 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1388 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1390 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1399 struct rtl8169_private *tp = netdev_priv(dev);
1402 wol->wolopts = tp->saved_wolopts;
1405 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1423 rtl_unlock_config_regs(tp);
1425 if (rtl_is_8168evl_up(tp)) {
1428 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1430 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1431 } else if (rtl_is_8125(tp)) {
1434 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1436 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1439 raw_spin_lock_irqsave(&tp->config25_lock, flags);
1441 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1444 RTL_W8(tp, cfg[i].reg, options);
1446 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1448 switch (tp->mac_version) {
1450 options = RTL_R8(tp, Config1) & ~PMEnable;
1453 RTL_W8(tp, Config1, options);
1459 rtl_mod_config2(tp, 0, PME_SIGNAL);
1461 rtl_mod_config2(tp, PME_SIGNAL, 0);
1467 rtl_lock_config_regs(tp);
1469 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1471 if (!tp->dash_enabled) {
1472 rtl_set_d3_pll_down(tp, !wolopts);
1473 tp->dev->wol_enabled = wolopts ? 1 : 0;
1479 struct rtl8169_private *tp = netdev_priv(dev);
1484 tp->saved_wolopts = wol->wolopts;
1485 __rtl8169_set_wol(tp, tp->saved_wolopts);
1493 struct rtl8169_private *tp = netdev_priv(dev);
1494 struct rtl_fw *rtl_fw = tp->rtl_fw;
1497 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1512 struct rtl8169_private *tp = netdev_priv(dev);
1518 tp->mac_version > RTL_GIGA_MAC_VER_06)
1524 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1527 u32 rx_config = RTL_R32(tp, RxConfig);
1534 if (rtl_is_8125(tp)) {
1541 RTL_W32(tp, RxConfig, rx_config);
1547 struct rtl8169_private *tp = netdev_priv(dev);
1549 rtl_set_rx_config_features(tp, features);
1552 tp->cp_cmd |= RxChkSum;
1554 tp->cp_cmd &= ~RxChkSum;
1556 if (!rtl_is_8125(tp)) {
1558 tp->cp_cmd |= RxVlan;
1560 tp->cp_cmd &= ~RxVlan;
1563 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1564 rtl_pci_commit(tp);
1586 struct rtl8169_private *tp = netdev_priv(dev);
1587 u32 __iomem *data = tp->mmio_addr;
1623 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1626 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1628 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1630 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1631 rtl_pci_commit(tp);
1632 RTL_W32(tp, CounterAddrLow, cmd);
1633 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1635 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1638 static void rtl8169_update_counters(struct rtl8169_private *tp)
1640 u8 val = RTL_R8(tp, ChipCmd);
1647 rtl8169_do_counters(tp, CounterDump);
1650 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1652 struct rtl8169_counters *counters = tp->counters;
1669 if (tp->tc_offset.inited)
1672 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1673 rtl8169_do_counters(tp, CounterReset);
1675 rtl8169_update_counters(tp);
1676 tp->tc_offset.tx_errors = counters->tx_errors;
1677 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1678 tp->tc_offset.tx_aborted = counters->tx_aborted;
1679 tp->tc_offset.rx_missed = counters->rx_missed;
1682 tp->tc_offset.inited = true;
1688 struct rtl8169_private *tp = netdev_priv(dev);
1691 counters = tp->counters;
1692 rtl8169_update_counters(tp);
1772 rtl_coalesce_info(struct rtl8169_private *tp)
1776 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1782 if (tp->phydev->speed == SPEED_UNKNOWN)
1786 if (tp->phydev->speed == ci->speed)
1798 struct rtl8169_private *tp = netdev_priv(dev);
1803 if (rtl_is_8125(tp))
1809 ci = rtl_coalesce_info(tp);
1813 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1815 intrmit = RTL_R16(tp, IntrMitigate);
1834 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1840 ci = rtl_coalesce_info(tp);
1859 struct rtl8169_private *tp = netdev_priv(dev);
1866 if (rtl_is_8125(tp))
1873 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1905 RTL_W16(tp, IntrMitigate, w);
1908 if (rtl_is_8168evl_up(tp)) {
1911 tp->cp_cmd |= PktCntrDisable;
1913 tp->cp_cmd &= ~PktCntrDisable;
1916 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1917 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1918 rtl_pci_commit(tp);
1925 struct rtl8169_private *tp = netdev_priv(dev);
1927 if (!rtl_supports_eee(tp))
1930 return phy_ethtool_get_eee(tp->phydev, data);
1935 struct rtl8169_private *tp = netdev_priv(dev);
1938 if (!rtl_supports_eee(tp))
1941 ret = phy_ethtool_set_eee(tp->phydev, data);
1944 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1963 struct rtl8169_private *tp = netdev_priv(dev);
1966 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1968 data->autoneg = tp->phydev->autoneg;
1976 struct rtl8169_private *tp = netdev_priv(dev);
1981 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2011 static void rtl_enable_eee(struct rtl8169_private *tp)
2013 struct phy_device *phydev = tp->phydev;
2017 if (tp->eee_adv >= 0)
2018 adv = tp->eee_adv;
2033 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2037 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2158 static void rtl_release_firmware(struct rtl8169_private *tp)
2160 if (tp->rtl_fw) {
2161 rtl_fw_release_firmware(tp->rtl_fw);
2162 kfree(tp->rtl_fw);
2163 tp->rtl_fw = NULL;
2167 void r8169_apply_firmware(struct rtl8169_private *tp)
2172 if (tp->rtl_fw) {
2173 rtl_fw_write_firmware(tp, tp->rtl_fw);
2174 /* At least one firmware doesn't reset tp->ocp_base. */
2175 tp->ocp_base = OCP_STD_PHY_BASE;
2178 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2184 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2187 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2188 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2190 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2193 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2195 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2196 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2199 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2201 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2204 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2206 rtl8125_set_eee_txidle_timer(tp);
2207 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2210 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2212 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2213 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2214 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2215 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2218 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2222 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2223 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2224 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2234 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2236 set_bit(flag, tp->wk.flags);
2237 schedule_work(&tp->wk.work);
2240 static void rtl8169_init_phy(struct rtl8169_private *tp)
2242 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2244 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2245 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2246 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2248 RTL_W8(tp, 0x82, 0x01);
2251 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2252 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2253 tp->pci_dev->subsystem_device == 0xe000)
2254 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2257 phy_speed_up(tp->phydev);
2259 if (rtl_supports_eee(tp))
2260 rtl_enable_eee(tp);
2262 genphy_soft_reset(tp->phydev);
2265 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2267 rtl_unlock_config_regs(tp);
2269 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2270 rtl_pci_commit(tp);
2272 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2273 rtl_pci_commit(tp);
2275 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2276 rtl_rar_exgmac_set(tp, addr);
2278 rtl_lock_config_regs(tp);
2283 struct rtl8169_private *tp = netdev_priv(dev);
2290 rtl_rar_set(tp, dev->dev_addr);
2295 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2297 switch (tp->mac_version) {
2300 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2305 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2308 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2311 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2314 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2318 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2323 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2325 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2328 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2334 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2336 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2337 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2340 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2345 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2347 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2350 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2352 RTL_W8(tp, MaxTxPacketSize, 0x24);
2353 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2354 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2357 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2359 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2360 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2361 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2364 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2366 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2369 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2371 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2374 static void rtl_jumbo_config(struct rtl8169_private *tp)
2376 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2379 rtl_unlock_config_regs(tp);
2380 switch (tp->mac_version) {
2384 r8168b_1_hw_jumbo_enable(tp);
2386 r8168b_1_hw_jumbo_disable(tp);
2392 r8168c_hw_jumbo_enable(tp);
2394 r8168c_hw_jumbo_disable(tp);
2399 r8168dp_hw_jumbo_enable(tp);
2401 r8168dp_hw_jumbo_disable(tp);
2405 r8168e_hw_jumbo_enable(tp);
2407 r8168e_hw_jumbo_disable(tp);
2412 rtl_lock_config_regs(tp);
2414 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2415 pcie_set_readrq(tp->pci_dev, readrq);
2420 tp->phydev->advertising);
2422 tp->phydev->advertising);
2423 phy_start_aneg(tp->phydev);
2429 return RTL_R8(tp, ChipCmd) & CmdReset;
2432 static void rtl_hw_reset(struct rtl8169_private *tp)
2434 RTL_W8(tp, ChipCmd, CmdReset);
2436 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2439 static void rtl_request_firmware(struct rtl8169_private *tp)
2444 if (tp->rtl_fw || !tp->fw_name)
2455 rtl_fw->fw_name = tp->fw_name;
2456 rtl_fw->dev = tp_to_dev(tp);
2461 tp->rtl_fw = rtl_fw;
2464 static void rtl_rx_close(struct rtl8169_private *tp)
2466 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2471 return RTL_R8(tp, TxPoll) & NPQ;
2476 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2481 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2487 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2490 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2492 switch (tp->mac_version) {
2494 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2495 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2498 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2501 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2502 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2503 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2510 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2512 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2515 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2517 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2519 rtl_wait_txrx_fifo_empty(tp);
2522 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2524 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2525 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2528 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2529 rtl_disable_rxdvgate(tp);
2532 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2534 if (tp->dash_enabled)
2537 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2538 tp->mac_version == RTL_GIGA_MAC_VER_33)
2539 rtl_ephy_write(tp, 0x19, 0xff64);
2541 if (device_may_wakeup(tp_to_dev(tp))) {
2542 phy_speed_down(tp->phydev, false);
2543 rtl_wol_enable_rx(tp);
2547 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2552 if (rtl_is_8168evl_up(tp))
2555 RTL_W32(tp, TxConfig, val);
2558 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2561 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2564 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2571 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2572 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2573 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2574 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2577 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2581 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2583 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2588 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2591 RTL_W32(tp, 0x7c, val);
2599 struct rtl8169_private *tp = netdev_priv(dev);
2608 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2621 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2628 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2629 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2631 tmp = RTL_R32(tp, RxConfig);
2632 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2637 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2640 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2642 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2644 RTL_W32(tp, CSIDR, value);
2645 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2648 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2651 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2653 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2655 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2658 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2659 RTL_R32(tp, CSIDR) : ~0;
2662 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2664 struct pci_dev *pdev = tp->pci_dev;
2677 netdev_notice_once(tp->dev,
2679 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2680 rtl_csi_write(tp, 0x070c, csi | val << 24);
2683 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2686 rtl_set_aspm_entry_latency(tp, 0x27);
2695 static void __rtl_ephy_init(struct rtl8169_private *tp,
2701 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2702 rtl_ephy_write(tp, e->offset, w);
2707 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2709 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2711 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2715 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2717 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2721 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2724 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2727 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2737 switch (tp->mac_version) {
2739 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2742 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2745 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2752 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2754 switch (tp->mac_version) {
2756 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2759 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2766 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2768 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2772 if (enable && tp->aspm_manageable) {
2776 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2777 tp->mac_version == RTL_GIGA_MAC_VER_43)
2780 rtl_mod_config5(tp, 0, ASPM_en);
2781 rtl_mod_config2(tp, 0, ClkReqEn);
2783 switch (tp->mac_version) {
2787 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2789 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2795 switch (tp->mac_version) {
2798 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2804 rtl_mod_config2(tp, ClkReqEn, 0);
2805 rtl_mod_config5(tp, ASPM_en, 0);
2809 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2815 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2816 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2819 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2823 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2824 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2827 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2829 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2832 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2834 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2836 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2838 rtl_disable_clock_request(tp);
2841 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2851 rtl_set_def_aspm_entry_latency(tp);
2853 rtl_ephy_init(tp, e_info_8168cp);
2855 __rtl_hw_start_8168cp(tp);
2858 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2860 rtl_set_def_aspm_entry_latency(tp);
2862 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2865 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2867 rtl_set_def_aspm_entry_latency(tp);
2869 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2872 RTL_W8(tp, DBG_REG, 0x20);
2875 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2883 rtl_set_def_aspm_entry_latency(tp);
2885 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2887 rtl_ephy_init(tp, e_info_8168c_1);
2889 __rtl_hw_start_8168cp(tp);
2892 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2899 rtl_set_def_aspm_entry_latency(tp);
2901 rtl_ephy_init(tp, e_info_8168c_2);
2903 __rtl_hw_start_8168cp(tp);
2906 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2908 rtl_set_def_aspm_entry_latency(tp);
2910 __rtl_hw_start_8168cp(tp);
2913 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2915 rtl_set_def_aspm_entry_latency(tp);
2917 rtl_disable_clock_request(tp);
2920 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2929 rtl_set_def_aspm_entry_latency(tp);
2931 rtl_ephy_init(tp, e_info_8168d_4);
2933 rtl_enable_clock_request(tp);
2936 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2954 rtl_set_def_aspm_entry_latency(tp);
2956 rtl_ephy_init(tp, e_info_8168e_1);
2958 rtl_disable_clock_request(tp);
2961 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2962 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2964 rtl_mod_config5(tp, Spi_en, 0);
2967 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2976 rtl_set_def_aspm_entry_latency(tp);
2978 rtl_ephy_init(tp, e_info_8168e_2);
2980 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2981 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2982 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2983 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2984 rtl_reset_packet_filter(tp);
2985 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2986 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2987 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2989 rtl_disable_clock_request(tp);
2991 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2993 rtl8168_config_eee_mac(tp);
2995 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2996 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2997 rtl_mod_config5(tp, Spi_en, 0);
3000 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3002 rtl_set_def_aspm_entry_latency(tp);
3004 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3005 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3006 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3007 rtl_reset_packet_filter(tp);
3008 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3009 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3010 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3011 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3013 rtl_disable_clock_request(tp);
3015 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3016 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3017 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3018 rtl_mod_config5(tp, Spi_en, 0);
3020 rtl8168_config_eee_mac(tp);
3023 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3034 rtl_hw_start_8168f(tp);
3036 rtl_ephy_init(tp, e_info_8168f_1);
3039 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3049 rtl_hw_start_8168f(tp);
3050 rtl_pcie_state_l2l3_disable(tp);
3052 rtl_ephy_init(tp, e_info_8168f_1);
3055 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3057 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3058 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3060 rtl_set_def_aspm_entry_latency(tp);
3062 rtl_reset_packet_filter(tp);
3063 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3065 rtl_disable_rxdvgate(tp);
3067 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3068 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3070 rtl8168_config_eee_mac(tp);
3072 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3073 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3075 rtl_pcie_state_l2l3_disable(tp);
3078 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3087 rtl_hw_start_8168g(tp);
3088 rtl_ephy_init(tp, e_info_8168g_1);
3091 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3105 rtl_hw_start_8168g(tp);
3106 rtl_ephy_init(tp, e_info_8168g_2);
3109 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3124 rtl_hw_start_8168g(tp);
3126 rtl_ephy_init(tp, e_info_8411_2);
3131 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3132 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3133 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3134 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3135 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3136 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3137 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3138 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3140 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3142 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3143 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3144 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3145 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3146 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3147 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3148 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3149 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3150 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3151 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3152 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3153 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3154 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3155 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3156 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3157 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3158 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3159 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3160 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3161 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3162 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3163 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3164 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3165 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3166 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3167 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3168 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3169 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3170 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3171 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3172 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3173 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3174 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3175 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3176 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3177 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3178 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3179 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3180 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3181 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3182 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3183 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3184 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3185 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3186 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3187 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3188 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3189 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3190 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3191 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3192 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3193 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3194 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3195 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3196 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3197 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3198 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3199 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3200 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3201 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3202 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3203 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3204 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3205 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3206 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3207 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3208 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3209 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3210 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3211 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3212 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3213 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3214 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3215 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3216 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3217 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3218 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3219 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3220 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3221 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3222 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3223 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3224 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3225 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3226 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3227 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3228 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3229 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3230 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3231 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3232 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3233 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3234 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3235 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3236 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3237 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3238 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3239 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3240 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3241 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3242 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3243 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3244 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3245 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3246 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3247 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3248 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3249 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3250 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3251 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3252 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3254 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3256 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3257 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3258 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3259 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3260 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3261 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3262 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3265 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3277 rtl_ephy_init(tp, e_info_8168h_1);
3279 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3280 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3282 rtl_set_def_aspm_entry_latency(tp);
3284 rtl_reset_packet_filter(tp);
3286 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3288 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3290 rtl_disable_rxdvgate(tp);
3292 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3293 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3295 rtl8168_config_eee_mac(tp);
3297 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3298 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3300 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3302 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3304 rtl_pcie_state_l2l3_disable(tp);
3306 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3312 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3315 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3316 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3317 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3318 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3320 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3321 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3322 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3323 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3326 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3328 rtl8168ep_stop_cmac(tp);
3330 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3331 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3333 rtl_set_def_aspm_entry_latency(tp);
3335 rtl_reset_packet_filter(tp);
3337 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3339 rtl_disable_rxdvgate(tp);
3341 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3342 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3344 rtl8168_config_eee_mac(tp);
3346 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3348 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3350 rtl_pcie_state_l2l3_disable(tp);
3353 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3362 rtl_ephy_init(tp, e_info_8168ep_3);
3364 rtl_hw_start_8168ep(tp);
3366 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3367 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3369 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3370 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3371 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3374 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3382 rtl8168ep_stop_cmac(tp);
3383 rtl_ephy_init(tp, e_info_8117);
3385 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3386 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3388 rtl_set_def_aspm_entry_latency(tp);
3390 rtl_reset_packet_filter(tp);
3392 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3394 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3396 rtl_disable_rxdvgate(tp);
3398 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3399 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3401 rtl8168_config_eee_mac(tp);
3403 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3404 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3406 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3408 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3410 rtl_pcie_state_l2l3_disable(tp);
3412 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3417 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3420 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3421 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3422 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3423 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3425 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3426 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3427 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3428 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3431 r8169_apply_firmware(tp);
3434 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3448 rtl_set_def_aspm_entry_latency(tp);
3450 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3452 RTL_W8(tp, Config1,
3454 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3456 cfg1 = RTL_R8(tp, Config1);
3458 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3460 rtl_ephy_init(tp, e_info_8102e_1);
3463 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3465 rtl_set_def_aspm_entry_latency(tp);
3467 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3468 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3471 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3473 rtl_hw_start_8102e_2(tp);
3475 rtl_ephy_write(tp, 0x03, 0xc2f9);
3478 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3487 rtl_ephy_init(tp, e_info_8401);
3488 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3491 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3505 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3508 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3510 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3511 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3513 rtl_ephy_init(tp, e_info_8105e_1);
3515 rtl_pcie_state_l2l3_disable(tp);
3518 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3520 rtl_hw_start_8105e_1(tp);
3521 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3524 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3531 rtl_set_def_aspm_entry_latency(tp);
3534 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3536 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3538 rtl_ephy_init(tp, e_info_8402);
3540 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3541 rtl_reset_packet_filter(tp);
3542 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3543 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3544 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3547 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3549 rtl_pcie_state_l2l3_disable(tp);
3552 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3555 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3557 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3558 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3559 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3562 rtl_set_aspm_entry_latency(tp, 0x2f);
3564 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3567 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3569 rtl_pcie_state_l2l3_disable(tp);
3574 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3577 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3579 rtl_pcie_state_l2l3_disable(tp);
3581 RTL_W16(tp, 0x382, 0x221b);
3582 RTL_W8(tp, 0x4500, 0);
3583 RTL_W16(tp, 0x4800, 0);
3586 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3588 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3590 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3591 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3593 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3594 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3595 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3598 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3600 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3601 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3603 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3605 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3606 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3608 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3610 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3611 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3612 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3613 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3614 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3615 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3616 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3617 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3618 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3620 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3621 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3623 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3624 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3626 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3628 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3630 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3631 rtl8125b_config_eee_mac(tp);
3633 rtl8125a_config_eee_mac(tp);
3635 rtl_disable_rxdvgate(tp);
3638 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3656 rtl_set_def_aspm_entry_latency(tp);
3657 rtl_ephy_init(tp, e_info_8125a_2);
3658 rtl_hw_start_8125_common(tp);
3661 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3672 rtl_set_def_aspm_entry_latency(tp);
3673 rtl_ephy_init(tp, e_info_8125b);
3674 rtl_hw_start_8125_common(tp);
3677 static void rtl_hw_config(struct rtl8169_private *tp)
3721 if (hw_configs[tp->mac_version])
3722 hw_configs[tp->mac_version](tp);
3725 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3731 RTL_W32(tp, i, 0);
3733 rtl_hw_config(tp);
3736 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3738 if (rtl_is_8168evl_up(tp))
3739 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3741 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3743 rtl_hw_config(tp);
3746 RTL_W16(tp, IntrMitigate, 0x0000);
3749 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3751 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3753 tp->cp_cmd |= PCIMulRW;
3755 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3756 tp->mac_version == RTL_GIGA_MAC_VER_03)
3757 tp->cp_cmd |= EnAnaPLL;
3759 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3761 rtl8169_set_magic_reg(tp);
3764 RTL_W16(tp, IntrMitigate, 0x0000);
3767 static void rtl_hw_start(struct rtl8169_private *tp)
3769 rtl_unlock_config_regs(tp);
3771 rtl_hw_aspm_clkreq_enable(tp, false);
3772 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3774 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3775 rtl_hw_start_8169(tp);
3776 else if (rtl_is_8125(tp))
3777 rtl_hw_start_8125(tp);
3779 rtl_hw_start_8168(tp);
3781 rtl_enable_exit_l1(tp);
3782 rtl_hw_aspm_clkreq_enable(tp, true);
3783 rtl_set_rx_max_size(tp);
3784 rtl_set_rx_tx_desc_registers(tp);
3785 rtl_lock_config_regs(tp);
3787 rtl_jumbo_config(tp);
3790 rtl_pci_commit(tp);
3792 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3793 rtl_init_rxcfg(tp);
3794 rtl_set_tx_config_registers(tp);
3795 rtl_set_rx_config_features(tp, tp->dev->features);
3796 rtl_set_rx_mode(tp->dev);
3797 rtl_irq_enable(tp);
3802 struct rtl8169_private *tp = netdev_priv(dev);
3806 rtl_jumbo_config(tp);
3808 switch (tp->mac_version) {
3811 rtl8125_set_eee_txidle_timer(tp);
3830 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3833 struct device *d = tp_to_dev(tp);
3844 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3855 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3859 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3860 dma_unmap_page(tp_to_dev(tp),
3861 le64_to_cpu(tp->RxDescArray[i].addr),
3863 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3864 tp->Rx_databuff[i] = NULL;
3865 tp->RxDescArray[i].addr = 0;
3866 tp->RxDescArray[i].opts1 = 0;
3870 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3877 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3879 rtl8169_rx_clear(tp);
3882 tp->Rx_databuff[i] = data;
3886 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3891 static int rtl8169_init_ring(struct rtl8169_private *tp)
3893 rtl8169_init_ring_indexes(tp);
3895 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3896 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3898 return rtl8169_rx_fill(tp);
3901 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3903 struct ring_info *tx_skb = tp->tx_skb + entry;
3904 struct TxDesc *desc = tp->TxDescArray + entry;
3906 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3912 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3919 struct ring_info *tx_skb = tp->tx_skb + entry;
3925 rtl8169_unmap_tx_skb(tp, entry);
3932 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3934 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3935 netdev_reset_queue(tp->dev);
3938 static void rtl8169_cleanup(struct rtl8169_private *tp)
3940 napi_disable(&tp->napi);
3946 rtl8169_irq_mask_and_ack(tp);
3948 rtl_rx_close(tp);
3950 switch (tp->mac_version) {
3953 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3956 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3957 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3960 rtl_enable_rxdvgate(tp);
3964 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3969 rtl_hw_reset(tp);
3971 rtl8169_tx_clear(tp);
3972 rtl8169_init_ring_indexes(tp);
3975 static void rtl_reset_work(struct rtl8169_private *tp)
3979 netif_stop_queue(tp->dev);
3981 rtl8169_cleanup(tp);
3984 rtl8169_mark_to_asic(tp->RxDescArray + i);
3986 napi_enable(&tp->napi);
3987 rtl_hw_start(tp);
3992 struct rtl8169_private *tp = netdev_priv(dev);
3994 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
3997 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4000 struct TxDesc *txd = tp->TxDescArray + entry;
4001 struct device *d = tp_to_dev(tp);
4010 netdev_err(tp->dev, "Failed to map TX data!\n");
4024 tp->tx_skb[entry].len = len;
4029 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4042 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4049 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4074 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4079 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4101 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4106 padto = rtl8125_quirk_udp_padto(tp, skb);
4108 switch (tp->mac_version) {
4140 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4189 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4198 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4200 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4204 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4206 switch (tp->mac_version) {
4215 static void rtl8169_doorbell(struct rtl8169_private *tp)
4217 if (rtl_is_8125(tp))
4218 RTL_W16(tp, TxPoll_8125, BIT(0));
4220 RTL_W8(tp, TxPoll, NPQ);
4227 struct rtl8169_private *tp = netdev_priv(dev);
4228 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4233 if (unlikely(!rtl_tx_slots_avail(tp))) {
4242 if (!rtl_chip_supports_csum_v2(tp))
4244 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4247 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4251 txd_first = tp->TxDescArray + entry;
4254 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4259 txd_last = tp->TxDescArray + entry;
4261 tp->tx_skb[entry].skb = skb;
4272 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4275 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4277 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4281 rtl8169_doorbell(tp);
4286 rtl8169_unmap_tx_skb(tp, entry);
4333 struct rtl8169_private *tp = netdev_priv(dev);
4336 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4340 rtl_chip_supports_csum_v2(tp))
4347 if (rtl_quirk_packet_padto(tp, skb))
4351 rtl_chip_supports_csum_v2(tp))
4360 struct rtl8169_private *tp = netdev_priv(dev);
4361 struct pci_dev *pdev = tp->pci_dev;
4373 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4376 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4382 dirty_tx = tp->dirty_tx;
4384 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4388 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4392 skb = tp->tx_skb[entry].skb;
4393 rtl8169_unmap_tx_skb(tp, entry);
4403 if (tp->dirty_tx != dirty_tx) {
4405 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4408 rtl_tx_slots_avail(tp),
4418 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4419 rtl8169_doorbell(tp);
4438 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4440 struct device *d = tp_to_dev(tp);
4443 for (count = 0; count < budget; count++, tp->cur_rx++) {
4444 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4445 struct RxDesc *desc = tp->RxDescArray + entry;
4490 skb = napi_alloc_skb(&tp->napi, pkt_size);
4497 rx_buf = page_address(tp->Rx_databuff[entry]);
4514 napi_gro_receive(&tp->napi, skb);
4526 struct rtl8169_private *tp = dev_instance;
4527 u32 status = rtl_get_events(tp);
4529 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4533 rtl8169_pcierr_interrupt(tp->dev);
4538 phy_mac_interrupt(tp->phydev);
4541 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4542 netif_stop_queue(tp->dev);
4543 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4546 if (napi_schedule_prep(&tp->napi)) {
4547 rtl_irq_disable(tp);
4548 __napi_schedule(&tp->napi);
4551 rtl_ack_events(tp, status);
4558 struct rtl8169_private *tp =
4564 if (!netif_running(tp->dev) ||
4565 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4568 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4570 if (RTL_R32(tp, TxConfig) == ~0) {
4571 ret = pci_reset_bus(tp->pci_dev);
4573 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4574 netif_device_detach(tp->dev);
4580 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4583 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4587 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4589 rtl_reset_work(tp);
4590 netif_wake_queue(tp->dev);
4591 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4592 rtl_reset_work(tp);
4600 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4601 struct net_device *dev = tp->dev;
4604 rtl_tx(dev, tp, budget);
4606 work_done = rtl_rx(dev, tp, budget);
4609 rtl_irq_enable(tp);
4616 struct rtl8169_private *tp = netdev_priv(ndev);
4617 struct device *d = tp_to_dev(tp);
4620 rtl_link_chg_patch(tp);
4622 netif_wake_queue(tp->dev);
4625 if (rtl_is_8125(tp))
4626 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4630 phy_print_status(tp->phydev);
4633 static int r8169_phy_connect(struct rtl8169_private *tp)
4635 struct phy_device *phydev = tp->phydev;
4639 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4642 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4647 if (!tp->supports_gmii)
4655 static void rtl8169_down(struct rtl8169_private *tp)
4658 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4660 phy_stop(tp->phydev);
4662 rtl8169_update_counters(tp);
4664 pci_clear_master(tp->pci_dev);
4665 rtl_pci_commit(tp);
4667 rtl8169_cleanup(tp);
4668 rtl_disable_exit_l1(tp);
4669 rtl_prepare_power_down(tp);
4671 if (tp->dash_type != RTL_DASH_NONE)
4672 rtl8168_driver_stop(tp);
4675 static void rtl8169_up(struct rtl8169_private *tp)
4677 if (tp->dash_type != RTL_DASH_NONE)
4678 rtl8168_driver_start(tp);
4680 pci_set_master(tp->pci_dev);
4681 phy_init_hw(tp->phydev);
4682 phy_resume(tp->phydev);
4683 rtl8169_init_phy(tp);
4684 napi_enable(&tp->napi);
4685 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4686 rtl_reset_work(tp);
4688 phy_start(tp->phydev);
4693 struct rtl8169_private *tp = netdev_priv(dev);
4694 struct pci_dev *pdev = tp->pci_dev;
4699 rtl8169_down(tp);
4700 rtl8169_rx_clear(tp);
4702 cancel_work(&tp->wk.work);
4704 free_irq(tp->irq, tp);
4706 phy_disconnect(tp->phydev);
4708 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4709 tp->RxPhyAddr);
4710 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4711 tp->TxPhyAddr);
4712 tp->TxDescArray = NULL;
4713 tp->RxDescArray = NULL;
4723 struct rtl8169_private *tp = netdev_priv(dev);
4725 rtl8169_interrupt(tp->irq, tp);
4731 struct rtl8169_private *tp = netdev_priv(dev);
4732 struct pci_dev *pdev = tp->pci_dev;
4742 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4743 &tp->TxPhyAddr, GFP_KERNEL);
4744 if (!tp->TxDescArray)
4747 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4748 &tp->RxPhyAddr, GFP_KERNEL);
4749 if (!tp->RxDescArray)
4752 retval = rtl8169_init_ring(tp);
4756 rtl_request_firmware(tp);
4759 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4763 retval = r8169_phy_connect(tp);
4767 rtl8169_up(tp);
4768 rtl8169_init_counter_offsets(tp);
4776 free_irq(tp->irq, tp);
4778 rtl_release_firmware(tp);
4779 rtl8169_rx_clear(tp);
4781 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4782 tp->RxPhyAddr);
4783 tp->RxDescArray = NULL;
4785 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4786 tp->TxPhyAddr);
4787 tp->TxDescArray = NULL;
4794 struct rtl8169_private *tp = netdev_priv(dev);
4795 struct pci_dev *pdev = tp->pci_dev;
4796 struct rtl8169_counters *counters = tp->counters;
4808 rtl8169_update_counters(tp);
4815 le64_to_cpu(tp->tc_offset.tx_errors);
4817 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4819 le16_to_cpu(tp->tc_offset.tx_aborted);
4821 le16_to_cpu(tp->tc_offset.rx_missed);
4826 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4828 netif_device_detach(tp->dev);
4830 if (netif_running(tp->dev))
4831 rtl8169_down(tp);
4836 struct rtl8169_private *tp = dev_get_drvdata(dev);
4838 rtl_rar_set(tp, tp->dev->dev_addr);
4839 __rtl8169_set_wol(tp, tp->saved_wolopts);
4841 if (tp->TxDescArray)
4842 rtl8169_up(tp);
4844 netif_device_attach(tp->dev);
4851 struct rtl8169_private *tp = dev_get_drvdata(device);
4854 rtl8169_net_suspend(tp);
4855 if (!device_may_wakeup(tp_to_dev(tp)))
4856 clk_disable_unprepare(tp->clk);
4864 struct rtl8169_private *tp = dev_get_drvdata(device);
4866 if (!device_may_wakeup(tp_to_dev(tp)))
4867 clk_prepare_enable(tp->clk);
4870 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4871 rtl_init_rxcfg(tp);
4878 struct rtl8169_private *tp = dev_get_drvdata(device);
4880 if (!tp->TxDescArray) {
4881 netif_device_detach(tp->dev);
4886 __rtl8169_set_wol(tp, WAKE_PHY);
4887 rtl8169_net_suspend(tp);
4895 struct rtl8169_private *tp = dev_get_drvdata(device);
4897 if (tp->dash_enabled)
4900 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4914 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4917 rtl8169_net_suspend(tp);
4921 rtl_rar_set(tp, tp->dev->perm_addr);
4923 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
4924 pci_wake_from_d3(pdev, tp->saved_wolopts);
4931 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4936 cancel_work_sync(&tp->wk.work);
4938 unregister_netdev(tp->dev);
4940 if (tp->dash_type != RTL_DASH_NONE)
4941 rtl8168_driver_stop(tp);
4943 rtl_release_firmware(tp);
4946 rtl_rar_set(tp, tp->dev->perm_addr);
4969 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4971 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4973 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4974 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4975 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4977 tp->irq_mask |= RxFIFOOver;
4979 tp->irq_mask |= RxOverflow;
4982 static int rtl_alloc_irq(struct rtl8169_private *tp)
4986 switch (tp->mac_version) {
4988 rtl_unlock_config_regs(tp);
4989 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4990 rtl_lock_config_regs(tp);
5000 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5003 static void rtl_read_mac_address(struct rtl8169_private *tp,
5007 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5010 value = rtl_eri_read(tp, 0xe0);
5012 value = rtl_eri_read(tp, 0xe4);
5014 } else if (rtl_is_8125(tp)) {
5015 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5021 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5024 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5026 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5031 struct rtl8169_private *tp = mii_bus->priv;
5036 return rtl_readphy(tp, phyreg);
5042 struct rtl8169_private *tp = mii_bus->priv;
5047 rtl_writephy(tp, phyreg, val);
5052 static int r8169_mdio_register(struct rtl8169_private *tp)
5054 struct pci_dev *pdev = tp->pci_dev;
5063 new_bus->priv = tp;
5076 tp->phydev = mdiobus_get_phy(new_bus, 0);
5077 if (!tp->phydev) {
5079 } else if (!tp->phydev->drv) {
5084 tp->phydev->phy_id);
5088 tp->phydev->mac_managed_pm = true;
5090 phy_support_asym_pause(tp->phydev);
5093 phy_suspend(tp->phydev);
5098 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5100 rtl_enable_rxdvgate(tp);
5102 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5104 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5106 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5107 r8168g_wait_ll_share_fifo_ready(tp);
5109 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5110 r8168g_wait_ll_share_fifo_ready(tp);
5113 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5115 rtl_enable_rxdvgate(tp);
5117 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5119 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5121 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5122 r8168g_wait_ll_share_fifo_ready(tp);
5124 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5125 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5126 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5127 r8168g_wait_ll_share_fifo_ready(tp);
5130 static void rtl_hw_initialize(struct rtl8169_private *tp)
5132 switch (tp->mac_version) {
5134 rtl8168ep_stop_cmac(tp);
5137 rtl_hw_init_8168g(tp);
5140 rtl_hw_init_8125(tp);
5147 static int rtl_jumbo_max(struct rtl8169_private *tp)
5150 if (!tp->supports_gmii)
5153 switch (tp->mac_version) {
5169 static void rtl_init_mac_address(struct rtl8169_private *tp)
5172 struct net_device *dev = tp->dev;
5175 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5179 rtl_read_mac_address(tp, mac_addr);
5183 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5189 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5192 rtl_rar_set(tp, mac_addr);
5196 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5198 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5199 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5207 struct rtl8169_private *tp;
5214 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5220 tp = netdev_priv(dev);
5221 tp->dev = dev;
5222 tp->pci_dev = pdev;
5223 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5224 tp->eee_adv = -1;
5225 tp->ocp_base = OCP_STD_PHY_BASE;
5227 raw_spin_lock_init(&tp->cfg9346_usage_lock);
5228 raw_spin_lock_init(&tp->config25_lock);
5229 raw_spin_lock_init(&tp->mac_ocp_lock);
5237 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5238 if (IS_ERR(tp->clk))
5239 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5258 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5260 txconfig = RTL_R32(tp, TxConfig);
5267 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5272 tp->mac_version = chipset;
5277 if (rtl_aspm_is_safe(tp))
5281 tp->aspm_manageable = !rc;
5283 tp->dash_type = rtl_get_dash_type(tp);
5284 tp->dash_enabled = rtl_dash_is_enabled(tp);
5286 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5288 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5292 rtl_init_rxcfg(tp);
5294 rtl8169_irq_mask_and_ack(tp);
5296 rtl_hw_initialize(tp);
5298 rtl_hw_reset(tp);
5300 rc = rtl_alloc_irq(tp);
5304 tp->irq = pci_irq_vector(pdev, 0);
5306 INIT_WORK(&tp->wk.work, rtl_task);
5308 rtl_init_mac_address(tp);
5312 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5323 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5327 if (rtl_chip_supports_csum_v2(tp))
5337 if (rtl_chip_supports_csum_v2(tp)) {
5355 if (!tp->dash_enabled) {
5356 rtl_set_d3_pll_down(tp, true);
5358 rtl_set_d3_pll_down(tp, false);
5362 jumbo_max = rtl_jumbo_max(tp);
5366 rtl_set_irq_mask(tp);
5368 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5370 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5371 &tp->counters_phys_addr,
5373 if (!tp->counters)
5376 pci_set_drvdata(pdev, tp);
5378 rc = r8169_mdio_register(tp);
5387 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5391 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5394 if (tp->dash_type != RTL_DASH_NONE) {
5396 tp->dash_enabled ? "enabled" : "disabled");
5397 rtl8168_driver_start(tp);