Lines Matching refs:value
108 u32 value;
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
115 if ((value & (sem_mask >> 16)) == sem_bits)
134 u32 value;
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
138 return ((value & (sem_mask >> 16)) == sem_bits);
177 u32 value;
181 value = readl(reg);
184 return value;
194 u32 value;
201 value = readl(reg);
204 return value;
215 u32 __iomem *reg, u32 value)
220 writel(value, reg);
226 u32 __iomem *reg, u32 value)
228 writel(value, reg);
233 u32 __iomem *reg, u32 value)
235 writel(value, reg);
241 u32 __iomem *reg, u32 value)
245 writel(value, reg);
253 u32 __iomem *reg, u32 value)
257 writel(value, reg);
265 u32 __iomem *reg, u32 value)
269 writel(value, reg);
368 unsigned short *value);
472 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
494 *value = (u16)data;
501 u32 eepromAddr, unsigned short *value)
505 fm93c56a_datain(qdev, value);
635 u16 regAddr, u16 value, u32 phyAddr)
651 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
666 u16 *value, u32 phyAddr)
696 *value = (u16) temp;
704 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
719 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
732 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
761 *value = (u16) temp;
1038 u32 value;
1041 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1043 value = (MAC_CONFIG_REG_PE << 16);
1046 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1048 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1058 u32 value;
1061 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1063 value = (MAC_CONFIG_REG_SR << 16);
1066 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1068 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1078 u32 value;
1081 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1083 value = (MAC_CONFIG_REG_GM << 16);
1086 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1088 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1098 u32 value;
1101 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1103 value = (MAC_CONFIG_REG_FD << 16);
1106 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1108 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1118 u32 value;
1121 value =
1125 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1128 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1130 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1346 be reinterpreted with a default value */
1752 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1755 qdev->msg_enable = value;
2206 u32 value;
2210 value = ql_read_common_reg_l(qdev,
2213 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2221 if (value & ISP_CONTROL_FE) {
2238 "Another function issued a reset to the chip. ISR value = %x\n",
2239 value);
2243 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2997 u32 value;
3122 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3123 if ((value & PORT_STATUS_IC) == 0) {
3131 value = qdev->nvram_data.tcpMaxWindowSize;
3132 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3134 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3142 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3212 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3213 if (value & PORT_STATUS_IC)
3228 value =
3233 ((value << 16) | value));
3235 value =
3239 ((value << 16) | value));
3255 u16 value;
3276 value =
3279 if ((value & ISP_CONTROL_SR) == 0)
3289 value =
3291 if (value & ISP_CONTROL_RI) {
3313 value = ql_read_common_reg(qdev,
3316 if ((value & ISP_CONTROL_FSR) == 0)
3333 u32 value, port_status;
3337 value =
3339 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3341 switch (value & ISP_CONTROL_FN_MASK) {
3369 value);
3613 u32 value;
3659 value = ql_read_common_reg(qdev,
3663 if ((value & ISP_CONTROL_SR) == 0) {
3669 if (value & ISP_CONTROL_RI) {
3686 if (value & ISP_CONTROL_SR) {
3720 u32 value;
3722 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3724 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3725 if (value & PORT_STATUS_64)
3729 if (value & PORT_STATUS_X)
3848 * Set the Maximum Memory Read Byte Count value. We do this to handle