Lines Matching defs:port_regs
106 struct ql3xxx_port_registers __iomem *port_regs =
113 &port_regs->CommonRegs.semaphoreReg);
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
124 struct ql3xxx_port_registers __iomem *port_regs =
126 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
127 readl(&port_regs->CommonRegs.semaphoreReg);
132 struct ql3xxx_port_registers __iomem *port_regs =
136 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
166 struct ql3xxx_port_registers __iomem *port_regs =
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
275 struct ql3xxx_port_registers __iomem *port_regs =
278 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
285 struct ql3xxx_port_registers __iomem *port_regs =
288 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
375 struct ql3xxx_port_registers __iomem *port_regs =
377 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
392 struct ql3xxx_port_registers __iomem *port_regs =
394 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
461 struct ql3xxx_port_registers __iomem *port_regs =
463 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
477 struct ql3xxx_port_registers __iomem *port_regs =
479 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
562 struct ql3xxx_port_registers __iomem *port_regs =
568 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
579 struct ql3xxx_port_registers __iomem *port_regs =
596 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
599 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
607 struct ql3xxx_port_registers __iomem *port_regs =
611 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
624 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
637 struct ql3xxx_port_registers __iomem *port_regs =
648 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
651 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
668 struct ql3xxx_port_registers __iomem *port_regs =
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
695 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
706 struct ql3xxx_port_registers __iomem *port_regs =
716 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
719 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
735 struct ql3xxx_port_registers __iomem *port_regs =
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
760 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
1036 struct ql3xxx_port_registers __iomem *port_regs =
1046 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1048 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1056 struct ql3xxx_port_registers __iomem *port_regs =
1066 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1068 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1076 struct ql3xxx_port_registers __iomem *port_regs =
1086 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1088 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1096 struct ql3xxx_port_registers __iomem *port_regs =
1106 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1108 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1116 struct ql3xxx_port_registers __iomem *port_regs =
1128 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1130 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1138 struct ql3xxx_port_registers __iomem *port_regs =
1152 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1168 struct ql3xxx_port_registers __iomem *port_regs =
1182 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1204 struct ql3xxx_port_registers __iomem *port_regs =
1217 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1242 struct ql3xxx_port_registers __iomem *port_regs =
1257 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1266 struct ql3xxx_port_registers __iomem *port_regs =
1272 &port_regs->CommonRegs.ispControlStatus,
1279 &port_regs->CommonRegs.ispControlStatus,
1296 struct ql3xxx_port_registers __iomem *port_regs =
1312 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1414 struct ql3xxx_port_registers __iomem *port_regs =
1428 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1615 struct ql3xxx_port_registers __iomem *port_regs =
1625 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1762 struct ql3xxx_port_registers __iomem *port_regs =
1767 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1845 struct ql3xxx_port_registers __iomem *port_regs =
1859 &port_regs->CommonRegs.rxSmallQProducerIndex);
1871 struct ql3xxx_port_registers __iomem *port_regs =
1912 &port_regs->CommonRegs.rxLargeQProducerIndex);
2178 struct ql3xxx_port_registers __iomem *port_regs =
2191 &port_regs->CommonRegs.rspQConsumerIndex);
2204 struct ql3xxx_port_registers __iomem *port_regs =
2211 &port_regs->CommonRegs.ispControlStatus);
2227 &port_regs->PortFatalErrStatus);
2460 struct ql3xxx_port_registers __iomem *port_regs =
2501 &port_regs->CommonRegs.reqQProducerIndex,
2998 struct ql3xxx_port_registers __iomem *port_regs =
3000 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3002 (void __iomem *)port_regs;
3109 &port_regs->CommonRegs.
3113 &port_regs->CommonRegs.
3122 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3132 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3142 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3143 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3152 &port_regs->mac1MaxFrameLengthReg,
3156 &port_regs->mac0MaxFrameLengthReg,
3173 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3175 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3182 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3184 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3189 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3194 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3197 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3199 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3202 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3208 &port_regs->portControl,
3212 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3232 ql_write_page0_reg(qdev, &port_regs->functionControl,
3238 ql_write_page0_reg(qdev, &port_regs->portControl,
3252 struct ql3xxx_port_registers __iomem *port_regs =
3266 &port_regs->CommonRegs.ispControlStatus,
3278 &port_regs->CommonRegs.ispControlStatus);
3290 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3295 &port_regs->CommonRegs.
3303 &port_regs->CommonRegs.
3314 &port_regs->CommonRegs.
3331 struct ql3xxx_port_registers __iomem *port_regs =
3338 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3340 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3560 struct ql3xxx_port_registers __iomem *port_regs =
3575 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3577 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3583 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3585 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3616 struct ql3xxx_port_registers __iomem *port_regs =
3651 &port_regs->CommonRegs.
3660 &port_regs->CommonRegs.
3673 &port_regs->
3718 struct ql3xxx_port_registers __iomem *port_regs =
3722 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);