Lines Matching refs:txreg
3307 u32 phyreg, txreg;
3342 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3344 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3346 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3348 writel(txreg, base + NvRegTxDeferral);
3351 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3355 txreg = NVREG_TX_WM_DESC2_3_1000;
3357 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3359 writel(txreg, base + NvRegTxWatermark);
3391 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3523 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3527 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3529 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3531 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3536 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3538 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3540 writel(txreg, base + NvRegTxDeferral);
3543 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3546 txreg = NVREG_TX_WM_DESC2_3_1000;
3548 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3550 writel(txreg, base + NvRegTxWatermark);
5716 u32 powerstate, txreg;
5891 txreg = readl(base + NvRegTransmitPoll);
5900 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5924 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);