Lines Matching refs:phyaddr
768 int phyaddr;
1185 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1194 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1219 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1241 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1243 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1245 if (mii_rw(dev, np->phyaddr,
1248 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1251 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1254 if (mii_rw(dev, np->phyaddr,
1266 phy_reserved = mii_rw(dev, np->phyaddr,
1269 if (mii_rw(dev, np->phyaddr,
1282 if (mii_rw(dev, np->phyaddr,
1285 phy_reserved = mii_rw(dev, np->phyaddr,
1289 if (mii_rw(dev, np->phyaddr,
1292 if (mii_rw(dev, np->phyaddr,
1306 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1309 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1311 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1313 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1316 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1318 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1328 if (mii_rw(dev, np->phyaddr,
1331 if (mii_rw(dev, np->phyaddr,
1334 phy_reserved = mii_rw(dev, np->phyaddr,
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1338 phy_reserved = mii_rw(dev, np->phyaddr,
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1344 if (mii_rw(dev, np->phyaddr,
1347 if (mii_rw(dev, np->phyaddr,
1350 phy_reserved = mii_rw(dev, np->phyaddr,
1354 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1356 phy_reserved = mii_rw(dev, np->phyaddr,
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1360 if (mii_rw(dev, np->phyaddr,
1363 if (mii_rw(dev, np->phyaddr,
1366 phy_reserved = mii_rw(dev, np->phyaddr,
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1370 phy_reserved = mii_rw(dev, np->phyaddr,
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1376 if (mii_rw(dev, np->phyaddr,
1379 if (mii_rw(dev, np->phyaddr,
1395 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1397 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1428 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1432 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1442 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1445 mii_control_1000 = mii_rw(dev, np->phyaddr,
1453 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1461 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1469 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1518 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1521 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1525 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
3314 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3398 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3411 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3412 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3447 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3448 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3452 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3453 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3520 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
4378 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4388 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4400 cmd->base.phy_address = np->phyaddr;
4424 if (cmd->base.phy_address != np->phyaddr) {
4483 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4497 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4500 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4504 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4509 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4520 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4527 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4546 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4550 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4552 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4555 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4568 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4629 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4639 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4841 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4847 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4851 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4853 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4882 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4892 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
5036 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5037 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5466 mii_rw(dev, np->phyaddr, MII_BMCR,
5467 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5552 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5665 mii_rw(dev, np->phyaddr, MII_BMCR,
5666 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
6050 int phyaddr = i & 0x1F;
6053 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
6066 np->phyaddr = phyaddr;
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
6168 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6169 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6173 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6176 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6178 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);