Lines Matching refs:base

752 /* in dev: base, irq */
794 void __iomem *base;
941 return ((struct fe_priv *)netdev_priv(dev))->base;
944 static inline void pci_push(u8 __iomem *base)
947 readl(base);
971 u8 __iomem *base = get_hwbase(dev);
973 pci_push(base);
979 } while ((readl(base + offset) & mask) != target);
999 u8 __iomem *base = get_hwbase(dev);
1003 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1005 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1012 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1013 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1055 u8 __iomem *base = get_hwbase(dev);
1060 powerstate = readl(base + NvRegPowerState2);
1065 writel(powerstate, base + NvRegPowerState2);
1104 u8 __iomem *base = get_hwbase(dev);
1106 writel(mask, base + NvRegIrqMask);
1112 u8 __iomem *base = get_hwbase(dev);
1115 writel(mask, base + NvRegIrqMask);
1118 writel(0, base + NvRegMSIIrqMask);
1119 writel(0, base + NvRegIrqMask);
1144 u8 __iomem *base = get_hwbase(dev);
1148 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1150 reg = readl(base + NvRegMIIControl);
1152 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1158 writel(value, base + NvRegMIIData);
1161 writel(reg, base + NvRegMIIControl);
1169 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1172 retval = readl(base + NvRegMIIData);
1229 u8 __iomem *base = get_hwbase(dev);
1230 u32 powerstate = readl(base + NvRegPowerState2);
1234 writel(powerstate, base + NvRegPowerState2);
1238 writel(powerstate, base + NvRegPowerState2);
1389 u8 __iomem *base = get_hwbase(dev);
1439 phyinterface = readl(base + NvRegPhyInterface);
1534 u8 __iomem *base = get_hwbase(dev);
1535 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1538 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1540 writel(rx_ctrl, base + NvRegReceiverControl);
1541 pci_push(base);
1543 writel(np->linkspeed, base + NvRegLinkSpeed);
1544 pci_push(base);
1548 writel(rx_ctrl, base + NvRegReceiverControl);
1549 pci_push(base);
1555 u8 __iomem *base = get_hwbase(dev);
1556 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1562 writel(rx_ctrl, base + NvRegReceiverControl);
1570 writel(0, base + NvRegLinkSpeed);
1576 u8 __iomem *base = get_hwbase(dev);
1577 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1582 writel(tx_ctrl, base + NvRegTransmitterControl);
1583 pci_push(base);
1589 u8 __iomem *base = get_hwbase(dev);
1590 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1596 writel(tx_ctrl, base + NvRegTransmitterControl);
1604 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1605 base + NvRegTransmitPoll);
1623 u8 __iomem *base = get_hwbase(dev);
1625 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1626 pci_push(base);
1628 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1629 pci_push(base);
1635 u8 __iomem *base = get_hwbase(dev);
1638 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1639 pci_push(base);
1642 temp1 = readl(base + NvRegMacAddrA);
1643 temp2 = readl(base + NvRegMacAddrB);
1644 temp3 = readl(base + NvRegTransmitPoll);
1646 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1647 pci_push(base);
1649 writel(0, base + NvRegMacReset);
1650 pci_push(base);
1654 writel(temp1, base + NvRegMacAddrA);
1655 writel(temp2, base + NvRegMacAddrB);
1656 writel(temp3, base + NvRegTransmitPoll);
1658 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1659 pci_push(base);
1666 u8 __iomem *base = get_hwbase(dev);
1671 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1672 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1673 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1674 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1675 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1676 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1677 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1678 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1679 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1680 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1681 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1682 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1683 np->estats.rx_runt += readl(base + NvRegRxRunt);
1684 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1685 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1686 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1687 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1688 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1689 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1690 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1691 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1712 np->estats.tx_deferral += readl(base + NvRegTxDef);
1713 np->estats.tx_packets += readl(base + NvRegTxFrame);
1714 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1715 np->estats.tx_pause += readl(base + NvRegTxPause);
1716 np->estats.rx_pause += readl(base + NvRegRxPause);
1717 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1722 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1723 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1724 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
2095 u8 __iomem *base = get_hwbase(dev);
2100 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2107 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2111 writel(reg, base + NvRegSlotTime);
2144 u8 __iomem *base = get_hwbase(dev);
2188 writel(temp, base + NvRegBackOffControl);
2197 writel(temp, base + NvRegBackOffControl);
2740 u8 __iomem *base = get_hwbase(dev);
2746 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2748 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2762 readl(base + i + 0), readl(base + i + 4),
2763 readl(base + i + 8), readl(base + i + 12),
2764 readl(base + i + 16), readl(base + i + 20),
2765 readl(base + i + 24), readl(base + i + 28));
3109 u8 __iomem *base = get_hwbase(dev);
3133 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3136 base + NvRegRingSizes);
3137 pci_push(base);
3139 pci_push(base);
3154 u8 __iomem *base = get_hwbase(dev);
3161 writel(mac[0], base + NvRegMacAddrA);
3162 writel(mac[1], base + NvRegMacAddrB);
3209 u8 __iomem *base = get_hwbase(dev);
3212 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3257 writel(addr[0], base + NvRegMulticastAddrA);
3258 writel(addr[1], base + NvRegMulticastAddrB);
3259 writel(mask[0], base + NvRegMulticastMaskA);
3260 writel(mask[1], base + NvRegMulticastMaskB);
3261 writel(pff, base + NvRegPacketFilterFlags);
3269 u8 __iomem *base = get_hwbase(dev);
3274 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3276 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3279 writel(pff, base + NvRegPacketFilterFlags);
3283 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3291 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3293 writel(pause_enable, base + NvRegTxPauseFrame);
3294 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3297 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3298 writel(regmisc, base + NvRegMisc1);
3306 u8 __iomem *base = get_hwbase(dev);
3317 phyreg = readl(base + NvRegSlotTime);
3325 writel(phyreg, base + NvRegSlotTime);
3328 phyreg = readl(base + NvRegPhyInterface);
3337 writel(phyreg, base + NvRegPhyInterface);
3348 writel(txreg, base + NvRegTxDeferral);
3359 writel(txreg, base + NvRegTxWatermark);
3362 base + NvRegMisc1);
3363 pci_push(base);
3364 writel(np->linkspeed, base + NvRegLinkSpeed);
3365 pci_push(base);
3382 u8 __iomem *base = get_hwbase(dev);
3490 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3494 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3500 phyreg = readl(base + NvRegSlotTime);
3507 writel(phyreg, base + NvRegSlotTime);
3510 phyreg = readl(base + NvRegPhyInterface);
3518 writel(phyreg, base + NvRegPhyInterface);
3540 writel(txreg, base + NvRegTxDeferral);
3550 writel(txreg, base + NvRegTxWatermark);
3553 base + NvRegMisc1);
3554 pci_push(base);
3555 writel(np->linkspeed, base + NvRegLinkSpeed);
3556 pci_push(base);
3622 u8 __iomem *base = get_hwbase(dev);
3625 miistat = readl(base + NvRegMIIStatus);
3626 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3639 u8 __iomem *base = np->base;
3641 writel(0, base + NvRegMSIIrqMask);
3642 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3678 u8 __iomem *base = get_hwbase(dev);
3681 np->events = readl(base + NvRegIrqStatus);
3682 writel(np->events, base + NvRegIrqStatus);
3684 np->events = readl(base + NvRegMSIXIrqStatus);
3685 writel(np->events, base + NvRegMSIXIrqStatus);
3696 writel(0, base + NvRegIrqMask);
3711 u8 __iomem *base = get_hwbase(dev);
3714 np->events = readl(base + NvRegIrqStatus);
3715 writel(np->events, base + NvRegIrqStatus);
3717 np->events = readl(base + NvRegMSIXIrqStatus);
3718 writel(np->events, base + NvRegMSIXIrqStatus);
3729 writel(0, base + NvRegIrqMask);
3740 u8 __iomem *base = get_hwbase(dev);
3746 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3747 writel(events, base + NvRegMSIXIrqStatus);
3759 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3760 pci_push(base);
3781 u8 __iomem *base = get_hwbase(dev);
3843 writel(np->irqmask, base + NvRegIrqMask);
3852 u8 __iomem *base = get_hwbase(dev);
3858 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3859 writel(events, base + NvRegMSIXIrqStatus);
3876 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3877 pci_push(base);
3897 u8 __iomem *base = get_hwbase(dev);
3903 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3904 writel(events, base + NvRegMSIXIrqStatus);
3928 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3929 pci_push(base);
3942 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3943 pci_push(base);
3964 u8 __iomem *base = get_hwbase(dev);
3968 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3969 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3971 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3972 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3974 pci_push(base);
3989 u8 __iomem *base = get_hwbase(dev);
4001 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
4008 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
4014 u8 __iomem *base = get_hwbase(dev);
4075 writel(0, base + NvRegMSIXMap0);
4076 writel(0, base + NvRegMSIXMap1);
4094 writel(0, base + NvRegMSIXMap0);
4095 writel(0, base + NvRegMSIXMap1);
4115 writel(0, base + NvRegMSIMap0);
4116 writel(0, base + NvRegMSIMap1);
4118 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4159 u8 __iomem *base = get_hwbase(dev);
4215 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4218 base + NvRegRingSizes);
4219 pci_push(base);
4221 pci_push(base);
4224 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4226 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4236 writel(mask, base + NvRegIrqMask);
4237 pci_push(base);
4313 u8 __iomem *base = get_hwbase(dev);
4324 writel(flags, base + NvRegWakeUpFlags);
4339 cmd->base.port = PORT_MII;
4365 cmd->base.duplex = DUPLEX_HALF;
4367 cmd->base.duplex = DUPLEX_FULL;
4370 cmd->base.duplex = DUPLEX_UNKNOWN;
4372 cmd->base.speed = speed;
4373 cmd->base.autoneg = np->autoneg;
4400 cmd->base.phy_address = np->phyaddr;
4416 u32 speed = cmd->base.speed;
4422 if (cmd->base.port != PORT_MII)
4424 if (cmd->base.phy_address != np->phyaddr) {
4429 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4440 } else if (cmd->base.autoneg == AUTONEG_DISABLE) {
4446 if (cmd->base.duplex != DUPLEX_HALF &&
4447 cmd->base.duplex != DUPLEX_FULL)
4477 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4529 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF)
4531 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL)
4533 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF)
4535 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL)
4596 u8 __iomem *base = get_hwbase(dev);
4603 rbuf[i] = readl(base + i*sizeof(u32));
4674 u8 __iomem *base = get_hwbase(dev);
4774 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4777 base + NvRegRingSizes);
4778 pci_push(base);
4780 pci_push(base);
4963 u8 __iomem *base = get_hwbase(dev);
4982 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5048 u8 __iomem *base = get_hwbase(dev);
5053 orig_read = readl(base + nv_registers_test[i].reg);
5058 writel(orig_read, base + nv_registers_test[i].reg);
5060 new_read = readl(base + nv_registers_test[i].reg);
5067 writel(orig_read, base + nv_registers_test[i].reg);
5077 u8 __iomem *base = get_hwbase(dev);
5085 save_poll_interval = readl(base+NvRegPollingInterval);
5099 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5100 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5116 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5118 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5127 writel(save_poll_interval, base + NvRegPollingInterval);
5128 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5140 u8 __iomem *base = get_hwbase(dev);
5153 filter_flags = readl(base + NvRegPacketFilterFlags);
5154 misc1_flags = readl(base + NvRegMisc1);
5164 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5165 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5168 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5171 base + NvRegRingSizes);
5172 pci_push(base);
5255 writel(misc1_flags, base + NvRegMisc1);
5256 writel(filter_flags, base + NvRegPacketFilterFlags);
5266 u8 __iomem *base = get_hwbase(dev);
5286 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5288 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5327 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5330 base + NvRegRingSizes);
5331 pci_push(base);
5333 pci_push(base);
5380 u8 __iomem *base = get_hwbase(dev);
5385 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5395 tx_ctrl = readl(base + NvRegTransmitterControl);
5397 writel(tx_ctrl, base + NvRegTransmitterControl);
5400 tx_ctrl = readl(base + NvRegTransmitterControl);
5415 u8 __iomem *base = get_hwbase(dev);
5420 tx_ctrl = readl(base + NvRegTransmitterControl);
5422 writel(tx_ctrl, base + NvRegTransmitterControl);
5431 u8 __iomem *base = get_hwbase(dev);
5432 u32 data_ready = readl(base + NvRegTransmitterControl);
5437 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5438 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5441 data_ready2 = readl(base + NvRegTransmitterControl);
5452 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5460 u8 __iomem *base = get_hwbase(dev);
5473 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5474 writel(0, base + NvRegMulticastAddrB);
5475 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5476 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5477 writel(0, base + NvRegPacketFilterFlags);
5479 writel(0, base + NvRegTransmitterControl);
5480 writel(0, base + NvRegReceiverControl);
5482 writel(0, base + NvRegAdapterControl);
5485 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5491 writel(0, base + NvRegLinkSpeed);
5492 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5494 writel(0, base + NvRegUnknownSetupReg6);
5501 base + NvRegRingSizes);
5503 writel(np->linkspeed, base + NvRegLinkSpeed);
5505 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5507 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5508 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5509 writel(np->vlanctl_bits, base + NvRegVlanControl);
5510 pci_push(base);
5511 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5518 writel(0, base + NvRegMIIMask);
5519 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5520 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5522 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5523 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5524 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5525 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5527 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5532 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5536 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5538 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5542 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5543 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5546 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5548 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5550 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5551 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5553 base + NvRegAdapterControl);
5554 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5555 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5557 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5559 i = readl(base + NvRegPowerState);
5561 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5563 pci_push(base);
5565 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5568 pci_push(base);
5569 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5570 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5571 pci_push(base);
5580 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5581 writel(0, base + NvRegMulticastAddrB);
5582 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5583 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5584 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5588 readl(base + NvRegMIIStatus);
5589 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5630 u8 __iomem *base;
5649 base = get_hwbase(dev);
5651 pci_push(base);
5661 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5714 u8 __iomem *base;
5842 np->base = ioremap(addr, np->register_size);
5843 if (!np->base)
5886 base = get_hwbase(dev);
5887 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5888 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5891 txreg = readl(base + NvRegTransmitPoll);
5924 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5949 writel(0, base + NvRegWakeUpFlags);
5956 powerstate = readl(base + NvRegPowerState2);
5961 writel(powerstate, base + NvRegPowerState2);
6017 writel(0, base + NvRegMIIMask);
6018 phystate = readl(base + NvRegAdapterControl);
6022 writel(phystate, base + NvRegAdapterControl);
6024 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
6028 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
6029 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
6034 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
6037 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
6143 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6186 u8 __iomem *base = get_hwbase(dev);
6191 writel(np->orig_mac[0], base + NvRegMacAddrA);
6192 writel(np->orig_mac[1], base + NvRegMacAddrB);
6193 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6194 base + NvRegTransmitPoll);
6226 u8 __iomem *base = get_hwbase(dev);
6237 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6247 u8 __iomem *base = get_hwbase(dev);
6252 writel(np->saved_config_space[i], base+i*sizeof(u32));