Lines Matching defs:events
782 u32 events;
3681 np->events = readl(base + NvRegIrqStatus);
3682 writel(np->events, base + NvRegIrqStatus);
3684 np->events = readl(base + NvRegMSIXIrqStatus);
3685 writel(np->events, base + NvRegMSIXIrqStatus);
3687 if (!(np->events & np->irqmask))
3714 np->events = readl(base + NvRegIrqStatus);
3715 writel(np->events, base + NvRegIrqStatus);
3717 np->events = readl(base + NvRegMSIXIrqStatus);
3718 writel(np->events, base + NvRegMSIXIrqStatus);
3720 if (!(np->events & np->irqmask))
3741 u32 events;
3746 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3747 writel(events, base + NvRegMSIXIrqStatus);
3748 netdev_dbg(dev, "tx irq events: %08x\n", events);
3749 if (!(events & np->irqmask))
3815 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3826 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3853 u32 events;
3858 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3859 writel(events, base + NvRegMSIXIrqStatus);
3860 netdev_dbg(dev, "rx irq events: %08x\n", events);
3861 if (!(events & np->irqmask))
3898 u32 events;
3903 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3904 writel(events, base + NvRegMSIXIrqStatus);
3905 netdev_dbg(dev, "irq events: %08x\n", events);
3906 if (!(events & np->irqmask))
3914 if (events & NVREG_IRQ_LINK) {
3925 if (events & NVREG_IRQ_RECOVER_ERROR) {
3965 u32 events;
3968 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3969 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3971 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3972 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3975 if (!(events & NVREG_IRQ_TIMER))
6480 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");