Lines Matching defs:bmcr
1476 * (certain phys need bmcr to be setup with reset)
3389 u32 bmcr;
3398 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3399 if (bmcr & BMCR_LOOPBACK) {
4478 int adv, bmcr;
4509 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4511 bmcr |= BMCR_ANENABLE;
4514 if (phy_reset(dev, bmcr)) {
4519 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4520 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4523 int adv, bmcr;
4555 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4556 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4558 bmcr |= BMCR_FULLDPLX;
4560 bmcr |= BMCR_SPEED100;
4563 if (phy_reset(dev, bmcr)) {
4568 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4613 int bmcr;
4629 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4631 bmcr |= BMCR_ANENABLE;
4633 if (phy_reset(dev, bmcr)) {
4638 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4639 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4807 int adv, bmcr;
4851 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4852 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4853 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);