Lines Matching refs:status
68 #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
121 u32 status;
396 u32 status;
405 err = nixge_dma_poll_timeout(priv, offset, status,
406 !(status & XAXIDMA_CR_RESET_MASK), 10,
465 unsigned int status = 0;
472 status = cur_p->status;
474 while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
476 cur_p->status = 0;
478 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
485 status = cur_p->status;
501 if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
585 cur_p->status = 0;
607 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK &&
615 length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
653 cur_p->status = 0;
674 u32 status, cr;
681 status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
683 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
685 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
702 unsigned int status;
706 status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
707 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
708 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
712 if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
716 if (status & XAXIDMA_IRQ_ERROR_MASK) {
720 netdev_err(ndev, "DMA Tx error 0x%x\n", status);
736 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
746 unsigned int status;
750 status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
751 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
753 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
762 if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
766 if (status & XAXIDMA_IRQ_ERROR_MASK) {
769 netdev_err(ndev, "DMA Rx error 0x%x\n", status);
785 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
808 cur_p->status = 0;
814 cur_p->status = 0;
1086 u32 status, tmp;
1098 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1099 !status, 10, 1000);
1105 status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1107 return status;
1114 u32 status, tmp;
1126 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1127 !status, 10, 1000);
1139 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1140 !status, 10, 1000);
1146 status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1148 return status;
1155 u32 status, tmp;
1168 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1169 !status, 10, 1000);
1180 u32 status, tmp;
1192 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1193 !status, 10, 1000);
1205 err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1206 !status, 10, 1000);