Lines Matching refs:bar0
1009 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1013 val64 = readq(&bar0->pci_mode);
1043 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1049 val64 = readq(&bar0->pci_mode);
1113 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1137 writeq(val64, &bar0->tti_data1_mem);
1162 writeq(val64, &bar0->tti_data2_mem);
1167 writeq(val64, &bar0->tti_command_mem);
1169 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1189 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1212 writeq(val64, &bar0->sw_reset);
1214 val64 = readq(&bar0->sw_reset);
1219 writeq(val64, &bar0->sw_reset);
1221 val64 = readq(&bar0->sw_reset);
1228 val64 = readq(&bar0->adapter_status);
1238 add = &bar0->mac_cfg;
1239 val64 = readq(&bar0->mac_cfg);
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1243 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1247 val64 = readq(&bar0->mac_int_mask);
1248 val64 = readq(&bar0->mc_int_mask);
1249 val64 = readq(&bar0->xgxs_int_mask);
1253 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1258 &bar0->dtx_control, UF);
1266 &bar0->dtx_control, UF);
1267 val64 = readq(&bar0->dtx_control);
1274 writeq(val64, &bar0->tx_fifo_partition_0);
1275 writeq(val64, &bar0->tx_fifo_partition_1);
1276 writeq(val64, &bar0->tx_fifo_partition_2);
1277 writeq(val64, &bar0->tx_fifo_partition_3);
1292 writeq(val64, &bar0->tx_fifo_partition_0);
1297 writeq(val64, &bar0->tx_fifo_partition_1);
1302 writeq(val64, &bar0->tx_fifo_partition_2);
1307 writeq(val64, &bar0->tx_fifo_partition_3);
1322 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1324 val64 = readq(&bar0->tx_fifo_partition_0);
1326 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1332 val64 = readq(&bar0->tx_pa_cfg);
1337 writeq(val64, &bar0->tx_pa_cfg);
1346 writeq(val64, &bar0->rx_queue_priority);
1395 writeq(val64, &bar0->rx_queue_cfg);
1404 writeq(val64, &bar0->tx_w_round_robin_0);
1405 writeq(val64, &bar0->tx_w_round_robin_1);
1406 writeq(val64, &bar0->tx_w_round_robin_2);
1407 writeq(val64, &bar0->tx_w_round_robin_3);
1408 writeq(val64, &bar0->tx_w_round_robin_4);
1412 writeq(val64, &bar0->tx_w_round_robin_0);
1413 writeq(val64, &bar0->tx_w_round_robin_1);
1414 writeq(val64, &bar0->tx_w_round_robin_2);
1415 writeq(val64, &bar0->tx_w_round_robin_3);
1417 writeq(val64, &bar0->tx_w_round_robin_4);
1421 writeq(val64, &bar0->tx_w_round_robin_0);
1423 writeq(val64, &bar0->tx_w_round_robin_1);
1425 writeq(val64, &bar0->tx_w_round_robin_2);
1427 writeq(val64, &bar0->tx_w_round_robin_3);
1429 writeq(val64, &bar0->tx_w_round_robin_4);
1433 writeq(val64, &bar0->tx_w_round_robin_0);
1434 writeq(val64, &bar0->tx_w_round_robin_1);
1435 writeq(val64, &bar0->tx_w_round_robin_2);
1436 writeq(val64, &bar0->tx_w_round_robin_3);
1438 writeq(val64, &bar0->tx_w_round_robin_4);
1442 writeq(val64, &bar0->tx_w_round_robin_0);
1444 writeq(val64, &bar0->tx_w_round_robin_1);
1446 writeq(val64, &bar0->tx_w_round_robin_2);
1448 writeq(val64, &bar0->tx_w_round_robin_3);
1450 writeq(val64, &bar0->tx_w_round_robin_4);
1454 writeq(val64, &bar0->tx_w_round_robin_0);
1456 writeq(val64, &bar0->tx_w_round_robin_1);
1458 writeq(val64, &bar0->tx_w_round_robin_2);
1460 writeq(val64, &bar0->tx_w_round_robin_3);
1462 writeq(val64, &bar0->tx_w_round_robin_4);
1466 writeq(val64, &bar0->tx_w_round_robin_0);
1468 writeq(val64, &bar0->tx_w_round_robin_1);
1470 writeq(val64, &bar0->tx_w_round_robin_2);
1472 writeq(val64, &bar0->tx_w_round_robin_3);
1474 writeq(val64, &bar0->tx_w_round_robin_4);
1478 writeq(val64, &bar0->tx_w_round_robin_0);
1479 writeq(val64, &bar0->tx_w_round_robin_1);
1480 writeq(val64, &bar0->tx_w_round_robin_2);
1481 writeq(val64, &bar0->tx_w_round_robin_3);
1483 writeq(val64, &bar0->tx_w_round_robin_4);
1488 val64 = readq(&bar0->tx_fifo_partition_0);
1490 writeq(val64, &bar0->tx_fifo_partition_0);
1499 writeq(val64, &bar0->rx_w_round_robin_0);
1500 writeq(val64, &bar0->rx_w_round_robin_1);
1501 writeq(val64, &bar0->rx_w_round_robin_2);
1502 writeq(val64, &bar0->rx_w_round_robin_3);
1503 writeq(val64, &bar0->rx_w_round_robin_4);
1506 writeq(val64, &bar0->rts_qos_steering);
1510 writeq(val64, &bar0->rx_w_round_robin_0);
1511 writeq(val64, &bar0->rx_w_round_robin_1);
1512 writeq(val64, &bar0->rx_w_round_robin_2);
1513 writeq(val64, &bar0->rx_w_round_robin_3);
1515 writeq(val64, &bar0->rx_w_round_robin_4);
1518 writeq(val64, &bar0->rts_qos_steering);
1522 writeq(val64, &bar0->rx_w_round_robin_0);
1524 writeq(val64, &bar0->rx_w_round_robin_1);
1526 writeq(val64, &bar0->rx_w_round_robin_2);
1528 writeq(val64, &bar0->rx_w_round_robin_3);
1530 writeq(val64, &bar0->rx_w_round_robin_4);
1533 writeq(val64, &bar0->rts_qos_steering);
1537 writeq(val64, &bar0->rx_w_round_robin_0);
1538 writeq(val64, &bar0->rx_w_round_robin_1);
1539 writeq(val64, &bar0->rx_w_round_robin_2);
1540 writeq(val64, &bar0->rx_w_round_robin_3);
1542 writeq(val64, &bar0->rx_w_round_robin_4);
1545 writeq(val64, &bar0->rts_qos_steering);
1549 writeq(val64, &bar0->rx_w_round_robin_0);
1551 writeq(val64, &bar0->rx_w_round_robin_1);
1553 writeq(val64, &bar0->rx_w_round_robin_2);
1555 writeq(val64, &bar0->rx_w_round_robin_3);
1557 writeq(val64, &bar0->rx_w_round_robin_4);
1560 writeq(val64, &bar0->rts_qos_steering);
1564 writeq(val64, &bar0->rx_w_round_robin_0);
1566 writeq(val64, &bar0->rx_w_round_robin_1);
1568 writeq(val64, &bar0->rx_w_round_robin_2);
1570 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1575 writeq(val64, &bar0->rts_qos_steering);
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1581 writeq(val64, &bar0->rx_w_round_robin_1);
1583 writeq(val64, &bar0->rx_w_round_robin_2);
1585 writeq(val64, &bar0->rx_w_round_robin_3);
1587 writeq(val64, &bar0->rx_w_round_robin_4);
1590 writeq(val64, &bar0->rts_qos_steering);
1594 writeq(val64, &bar0->rx_w_round_robin_0);
1595 writeq(val64, &bar0->rx_w_round_robin_1);
1596 writeq(val64, &bar0->rx_w_round_robin_2);
1597 writeq(val64, &bar0->rx_w_round_robin_3);
1599 writeq(val64, &bar0->rx_w_round_robin_4);
1602 writeq(val64, &bar0->rts_qos_steering);
1609 writeq(val64, &bar0->rts_frm_len_n[i]);
1614 writeq(val64, &bar0->rts_frm_len_n[i]);
1628 &bar0->rts_frm_len_n[i]);
1643 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1647 writeq(val64, &bar0->stat_byte_cnt);
1656 writeq(val64, &bar0->mac_link_util);
1682 writeq(val64, &bar0->rti_data1_mem);
1692 writeq(val64, &bar0->rti_data2_mem);
1698 writeq(val64, &bar0->rti_command_mem);
1709 val64 = readq(&bar0->rti_command_mem);
1727 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1728 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1731 add = &bar0->mac_cfg;
1732 val64 = readq(&bar0->mac_cfg);
1734 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1736 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1738 val64 = readq(&bar0->mac_cfg);
1741 add = &bar0->mac_cfg;
1742 val64 = readq(&bar0->mac_cfg);
1745 writeq(val64, &bar0->mac_cfg);
1747 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1749 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1757 val64 = readq(&bar0->rmac_pause_cfg);
1760 writeq(val64, &bar0->rmac_pause_cfg);
1774 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1782 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1788 val64 = readq(&bar0->pic_control);
1790 writeq(val64, &bar0->pic_control);
1793 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1794 writeq(0x0, &bar0->read_retry_delay);
1795 writeq(0x0, &bar0->write_retry_delay);
1805 writeq(val64, &bar0->misc_control);
1806 val64 = readq(&bar0->pic_control2);
1808 writeq(val64, &bar0->pic_control2);
1812 writeq(val64, &bar0->tmac_avg_ipg);
1852 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1856 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1863 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1868 &bar0->pfc_err_mask);
1872 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1880 flag, &bar0->pcc_err_mask);
1883 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1888 flag, &bar0->lso_err_mask);
1891 flag, &bar0->tpa_err_mask);
1893 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1899 &bar0->mac_int_mask);
1903 flag, &bar0->mac_tmac_err_mask);
1909 &bar0->xgxs_int_mask);
1912 flag, &bar0->xgxs_txgxs_err_mask);
1919 flag, &bar0->rxdma_int_mask);
1923 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1927 &bar0->prc_pcix_err_mask);
1930 &bar0->rpa_err_mask);
1936 flag, &bar0->rda_err_mask);
1939 flag, &bar0->rti_err_mask);
1945 &bar0->mac_int_mask);
1952 flag, &bar0->mac_rmac_err_mask);
1958 &bar0->xgxs_int_mask);
1960 &bar0->xgxs_rxgxs_err_mask);
1966 flag, &bar0->mc_int_mask);
1969 &bar0->mc_err_mask);
1990 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2010 &bar0->pic_int_mask);
2012 &bar0->gpio_int_mask);
2014 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2020 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2032 writeq(0x0, &bar0->tx_traffic_mask);
2038 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2047 writeq(0x0, &bar0->rx_traffic_mask);
2053 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2057 temp64 = readq(&bar0->general_int_mask);
2062 writeq(temp64, &bar0->general_int_mask);
2064 nic->general_int_mask = readq(&bar0->general_int_mask);
2078 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2079 u64 val64 = readq(&bar0->adapter_status);
2120 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2121 u64 val64 = readq(&bar0->adapter_status);
2186 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2190 writeq(fix_mac[i++], &bar0->gpio_control);
2192 (void) readq(&bar0->gpio_control);
2211 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2223 &bar0->prc_rxd0_n[i]);
2225 val64 = readq(&bar0->prc_ctrl_n[i]);
2234 writeq(val64, &bar0->prc_ctrl_n[i]);
2239 val64 = readq(&bar0->rx_pa_cfg);
2241 writeq(val64, &bar0->rx_pa_cfg);
2245 val64 = readq(&bar0->rx_pa_cfg);
2247 writeq(val64, &bar0->rx_pa_cfg);
2256 val64 = readq(&bar0->mc_rldram_mrs);
2258 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2259 val64 = readq(&bar0->mc_rldram_mrs);
2264 val64 = readq(&bar0->adapter_control);
2266 writeq(val64, &bar0->adapter_control);
2272 val64 = readq(&bar0->adapter_status);
2289 val64 = readq(&bar0->adapter_control);
2291 writeq(val64, &bar0->adapter_control);
2304 val64 = readq(&bar0->gpio_control);
2306 writeq(val64, &bar0->gpio_control);
2308 writeq(val64, (void __iomem *)bar0 + 0x2700);
2414 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2425 val64 = readq(&bar0->adapter_control);
2427 writeq(val64, &bar0->adapter_control);
2768 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2780 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2794 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2814 writeq(0, &bar0->rx_traffic_mask);
2815 readl(&bar0->rx_traffic_mask);
2834 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2845 writeq(val64, &bar0->rx_traffic_int);
2846 writeq(val64, &bar0->tx_traffic_int);
3090 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3096 writeq(val64, &bar0->mdio_control);
3098 writeq(val64, &bar0->mdio_control);
3107 writeq(val64, &bar0->mdio_control);
3109 writeq(val64, &bar0->mdio_control);
3116 writeq(val64, &bar0->mdio_control);
3118 writeq(val64, &bar0->mdio_control);
3136 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3142 writeq(val64, &bar0->mdio_control);
3144 writeq(val64, &bar0->mdio_control);
3152 writeq(val64, &bar0->mdio_control);
3154 writeq(val64, &bar0->mdio_control);
3158 rval64 = readq(&bar0->mdio_control);
3402 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3419 writeq(val64, &bar0->sw_reset);
3459 writeq(s2BIT(62), &bar0->txpic_int_reg);
3494 val64 = readq(&bar0->gpio_control);
3496 writeq(val64, &bar0->gpio_control);
3498 writeq(val64, (void __iomem *)bar0 + 0x2700);
3506 val64 = readq(&bar0->pcc_err_reg);
3507 writeq(val64, &bar0->pcc_err_reg);
3526 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3534 val64 = readq(&bar0->pif_rd_swapper_fb);
3545 writeq(value[i], &bar0->swapper_ctrl);
3546 val64 = readq(&bar0->pif_rd_swapper_fb);
3559 valr = readq(&bar0->swapper_ctrl);
3563 writeq(valt, &bar0->xmsi_address);
3564 val64 = readq(&bar0->xmsi_address);
3576 writeq((value[i] | valr), &bar0->swapper_ctrl);
3577 writeq(valt, &bar0->xmsi_address);
3578 val64 = readq(&bar0->xmsi_address);
3590 val64 = readq(&bar0->swapper_ctrl);
3611 writeq(val64, &bar0->swapper_ctrl);
3635 writeq(val64, &bar0->swapper_ctrl);
3637 val64 = readq(&bar0->swapper_ctrl);
3643 val64 = readq(&bar0->pif_rd_swapper_fb);
3657 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3662 val64 = readq(&bar0->xmsi_access);
3678 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3687 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3688 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3690 writeq(val64, &bar0->xmsi_access);
3699 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3710 writeq(val64, &bar0->xmsi_access);
3716 addr = readq(&bar0->xmsi_address);
3717 data = readq(&bar0->xmsi_data);
3727 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3771 rx_mat = readq(&bar0->rx_mat);
3779 writeq(rx_mat, &bar0->rx_mat);
3780 readq(&bar0->rx_mat);
3824 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3839 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3843 writeq(val64, &bar0->scheduled_int_ctrl);
3858 writeq(saved64, &bar0->scheduled_int_ctrl);
4208 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4217 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4236 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4243 reason = readq(&bar0->general_int_status);
4249 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4255 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4260 writeq(sp->general_int_mask, &bar0->general_int_mask);
4261 readl(&bar0->general_int_status);
4270 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4273 val64 = readq(&bar0->pic_int_status);
4275 val64 = readq(&bar0->gpio_int_reg);
4284 writeq(val64, &bar0->gpio_int_reg);
4285 val64 = readq(&bar0->gpio_int_mask);
4288 writeq(val64, &bar0->gpio_int_mask);
4290 val64 = readq(&bar0->adapter_status);
4292 val64 = readq(&bar0->adapter_control);
4294 writeq(val64, &bar0->adapter_control);
4296 writeq(val64, &bar0->adapter_control);
4305 val64 = readq(&bar0->gpio_int_mask);
4308 writeq(val64, &bar0->gpio_int_mask);
4311 val64 = readq(&bar0->adapter_status);
4314 val64 = readq(&bar0->gpio_int_mask);
4317 writeq(val64, &bar0->gpio_int_mask);
4320 val64 = readq(&bar0->adapter_control);
4322 writeq(val64, &bar0->adapter_control);
4325 val64 = readq(&bar0->gpio_int_mask);
4364 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4392 val64 = readq(&bar0->mac_rmac_err_reg);
4393 writeq(val64, &bar0->mac_rmac_err_reg);
4399 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4404 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4410 val64 = readq(&bar0->ring_bump_counter1);
4417 val64 = readq(&bar0->ring_bump_counter2);
4425 val64 = readq(&bar0->txdma_int_status);
4431 &bar0->pfc_err_reg,
4435 &bar0->pfc_err_reg,
4444 &bar0->tda_err_reg,
4448 &bar0->tda_err_reg,
4458 &bar0->pcc_err_reg,
4462 &bar0->pcc_err_reg,
4469 &bar0->tti_err_reg,
4473 &bar0->tti_err_reg,
4481 &bar0->lso_err_reg,
4485 &bar0->lso_err_reg,
4492 &bar0->tpa_err_reg,
4496 &bar0->tpa_err_reg,
4503 &bar0->sm_err_reg,
4508 val64 = readq(&bar0->mac_int_status);
4511 &bar0->mac_tmac_err_reg,
4517 &bar0->mac_tmac_err_reg,
4521 val64 = readq(&bar0->xgxs_int_status);
4524 &bar0->xgxs_txgxs_err_reg,
4528 &bar0->xgxs_txgxs_err_reg,
4532 val64 = readq(&bar0->rxdma_int_status);
4538 &bar0->rc_err_reg,
4543 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4548 &bar0->prc_pcix_err_reg,
4554 &bar0->prc_pcix_err_reg,
4560 &bar0->rpa_err_reg,
4564 &bar0->rpa_err_reg,
4574 &bar0->rda_err_reg,
4581 &bar0->rda_err_reg,
4587 &bar0->rti_err_reg,
4591 &bar0->rti_err_reg,
4595 val64 = readq(&bar0->mac_int_status);
4598 &bar0->mac_rmac_err_reg,
4604 &bar0->mac_rmac_err_reg,
4608 val64 = readq(&bar0->xgxs_int_status);
4611 &bar0->xgxs_rxgxs_err_reg,
4616 val64 = readq(&bar0->mc_int_status);
4619 &bar0->mc_err_reg,
4625 writeq(val64, &bar0->mc_err_reg);
4666 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4689 reason = readq(&bar0->general_int_status);
4696 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4701 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4702 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4703 readl(&bar0->rx_traffic_int);
4712 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4727 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4745 writeq(sp->general_int_mask, &bar0->general_int_mask);
4746 readl(&bar0->general_int_status);
4763 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4771 writeq(val64, &bar0->stat_cfg);
4774 val64 = readq(&bar0->stat_cfg);
4891 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4901 &bar0->rmac_addr_data0_mem);
4903 &bar0->rmac_addr_data1_mem);
4907 writeq(val64, &bar0->rmac_addr_cmd_mem);
4909 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4918 &bar0->rmac_addr_data0_mem);
4920 &bar0->rmac_addr_data1_mem);
4924 writeq(val64, &bar0->rmac_addr_cmd_mem);
4926 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4936 add = &bar0->mac_cfg;
4937 val64 = readq(&bar0->mac_cfg);
4940 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4942 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4946 val64 = readq(&bar0->rx_pa_cfg);
4948 writeq(val64, &bar0->rx_pa_cfg);
4952 val64 = readq(&bar0->mac_cfg);
4958 add = &bar0->mac_cfg;
4959 val64 = readq(&bar0->mac_cfg);
4962 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4964 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4968 val64 = readq(&bar0->rx_pa_cfg);
4970 writeq(val64, &bar0->rx_pa_cfg);
4974 val64 = readq(&bar0->mac_cfg);
4996 &bar0->rmac_addr_data0_mem);
4998 &bar0->rmac_addr_data1_mem);
5003 writeq(val64, &bar0->rmac_addr_cmd_mem);
5006 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5026 &bar0->rmac_addr_data0_mem);
5028 &bar0->rmac_addr_data1_mem);
5033 writeq(val64, &bar0->rmac_addr_cmd_mem);
5036 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5126 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5129 &bar0->rmac_addr_data0_mem);
5133 writeq(val64, &bar0->rmac_addr_cmd_mem);
5136 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5172 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5177 writeq(val64, &bar0->rmac_addr_cmd_mem);
5180 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5186 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5374 reg = readq(sp->bar0 + i);
5384 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5390 val64 = readq(&bar0->gpio_control);
5396 writeq(val64, &bar0->gpio_control);
5398 val64 = readq(&bar0->adapter_control);
5404 writeq(val64, &bar0->adapter_control);
5425 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5429 u64 val64 = readq(&bar0->adapter_control);
5438 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5451 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5501 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5503 val64 = readq(&bar0->rmac_pause_cfg);
5527 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5529 val64 = readq(&bar0->rmac_pause_cfg);
5538 writeq(val64, &bar0->rmac_pause_cfg);
5563 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5571 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5574 val64 = readq(&bar0->i2c_control);
5589 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5591 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5593 val64 = readq(&bar0->spi_control);
5598 *data = readq(&bar0->spi_data);
5629 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5637 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5640 val64 = readq(&bar0->i2c_control);
5653 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5658 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5660 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5662 val64 = readq(&bar0->spi_control);
5848 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5852 val64 = readq(&bar0->pif_rd_swapper_fb);
5858 val64 = readq(&bar0->rmac_pause_cfg);
5864 val64 = readq(&bar0->rx_queue_cfg);
5874 val64 = readq(&bar0->xgxs_efifo_cfg);
5881 writeq(val64, &bar0->xmsi_data);
5882 val64 = readq(&bar0->xmsi_data);
5889 writeq(val64, &bar0->xmsi_data);
5890 val64 = readq(&bar0->xmsi_data);
6053 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6056 val64 = readq(&bar0->adapter_status);
6080 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6084 val64 = readq(&bar0->adapter_control);
6086 writeq(val64, &bar0->adapter_control);
6088 val64 = readq(&bar0->mc_rldram_test_ctrl);
6090 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6092 val64 = readq(&bar0->mc_rldram_mrs);
6094 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6097 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6103 writeq(val64, &bar0->mc_rldram_test_d0);
6108 writeq(val64, &bar0->mc_rldram_test_d1);
6113 writeq(val64, &bar0->mc_rldram_test_d2);
6116 writeq(val64, &bar0->mc_rldram_test_add);
6121 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6124 val64 = readq(&bar0->mc_rldram_test_ctrl);
6134 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6137 val64 = readq(&bar0->mc_rldram_test_ctrl);
6146 val64 = readq(&bar0->mc_rldram_test_ctrl);
6156 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6651 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6654 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6671 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6694 val64 = readq(&bar0->adapter_status);
6696 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6698 val64 = readq(&bar0->adapter_control);
6700 writeq(val64, &bar0->adapter_control);
6703 val64 = readq(&bar0->gpio_control);
6705 writeq(val64, &bar0->gpio_control);
6706 val64 = readq(&bar0->gpio_control);
6709 writeq(val64, &bar0->adapter_control);
6719 val64 = readq(&bar0->adapter_control);
6721 writeq(val64, &bar0->adapter_control);
6726 val64 = readq(&bar0->gpio_control);
6728 writeq(val64, &bar0->gpio_control);
6729 val64 = readq(&bar0->gpio_control);
6732 val64 = readq(&bar0->adapter_control);
6734 writeq(val64, &bar0->adapter_control);
7013 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7058 val64 = readq(&bar0->adapter_status);
7607 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7614 writeq(val64, &bar0->rts_ds_mem_data);
7620 writeq(val64, &bar0->rts_ds_mem_ctrl);
7622 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7666 struct XENA_dev_config __iomem *bar0 = NULL;
7835 sp->bar0 = pci_ioremap_bar(pdev, 0);
7836 if (!sp->bar0) {
7931 bar0 = sp->bar0;
7934 writeq(val64, &bar0->rmac_addr_cmd_mem);
7935 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7938 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8000 val64 = readq(&bar0->gpio_control);
8002 writeq(val64, &bar0->gpio_control);
8004 writeq(val64, (void __iomem *)bar0 + 0x2700);
8005 val64 = readq(&bar0->gpio_control);
8117 iounmap(sp->bar0);
8155 iounmap(sp->bar0);