Lines Matching defs:config
500 if (!sp->config.multiq) {
503 for (i = 0; i < sp->config.tx_fifo_num; i++)
511 if (!sp->config.multiq)
520 if (!sp->config.multiq) {
523 for (i = 0; i < sp->config.tx_fifo_num; i++)
531 if (!sp->config.multiq) {
534 for (i = 0; i < sp->config.tx_fifo_num; i++)
574 struct config_param *config = &nic->config;
580 for (i = 0; i < config->tx_fifo_num; i++) {
581 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
593 for (i = 0; i < config->tx_fifo_num; i++) {
594 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
608 lst_size = (sizeof(struct TxD) * config->max_txds);
611 for (i = 0; i < config->tx_fifo_num; i++) {
613 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
624 for (i = 0; i < config->tx_fifo_num; i++) {
625 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
628 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 for (i = 0; i < config->tx_fifo_num; i++) {
686 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
697 for (i = 0; i < config->rx_ring_num; i++) {
698 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
717 for (i = 0; i < config->rx_ring_num; i++) {
718 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
789 for (i = 0; i < config->rx_ring_num; i++) {
790 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
877 struct config_param *config;
887 config = &nic->config;
892 lst_size = sizeof(struct TxD) * config->max_txds;
895 for (i = 0; i < config->tx_fifo_num; i++) {
897 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
934 for (i = 0; i < config->rx_ring_num; i++) {
954 for (i = 0; i < config->rx_ring_num; i++) {
955 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
984 for (i = 0; i < nic->config.tx_fifo_num; i++) {
986 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1046 struct config_param *config = &nic->config;
1055 config->bus_speed = bus_speed[mode];
1116 struct config_param *config = &nic->config;
1118 for (i = 0; i < config->tx_fifo_num; i++) {
1125 int count = (nic->config.bus_speed * 125)/2;
1139 if (nic->config.intr_type == MSI_X) {
1145 if ((nic->config.tx_steering_type ==
1147 (config->tx_fifo_num > 1) &&
1198 struct config_param *config = &nic->config;
1279 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1280 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1285 if (i == (config->tx_fifo_num - 1)) {
1341 for (i = 0; i < config->rx_ring_num; i++) {
1342 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1358 for (i = 0; i < config->rx_ring_num; i++) {
1361 mem_share = (mem_size / config->rx_ring_num +
1362 mem_size % config->rx_ring_num);
1366 mem_share = (mem_size / config->rx_ring_num);
1370 mem_share = (mem_size / config->rx_ring_num);
1374 mem_share = (mem_size / config->rx_ring_num);
1378 mem_share = (mem_size / config->rx_ring_num);
1382 mem_share = (mem_size / config->rx_ring_num);
1386 mem_share = (mem_size / config->rx_ring_num);
1390 mem_share = (mem_size / config->rx_ring_num);
1401 switch (config->tx_fifo_num) {
1496 switch (config->rx_ring_num) {
1613 for (i = 0 ; i < config->rx_ring_num ; i++)
1619 for (i = 0; i < config->rx_ring_num; i++) {
1673 int count = (nic->config.bus_speed * 125)/4;
1686 if (nic->config.intr_type == MSI_X)
1694 for (i = 0; i < config->rx_ring_num; i++) {
1792 if (nic->config.bus_speed == 266) {
2215 struct config_param *config = &nic->config;
2219 for (i = 0; i < config->rx_ring_num; i++) {
2373 struct config_param *config = &nic->config;
2378 for (i = 0; i < config->tx_fifo_num; i++) {
2379 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2719 struct config_param *config = &sp->config;
2722 for (i = 0; i < config->rx_ring_num; i++) {
2796 struct config_param *config = &nic->config;
2802 for (i = 0; i < config->rx_ring_num; i++) {
2837 struct config_param *config = &nic->config;
2852 for (i = 0; i < config->tx_fifo_num; i++)
2856 for (i = 0; i < config->rx_ring_num; i++) {
2862 for (i = 0; i < config->rx_ring_num; i++) {
2960 if (ring_data->nic->config.napi) {
3070 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3609 if (sp->config.intr_type == INTA)
3633 if (sp->config.intr_type == INTA)
3772 for (j = 0; j < nic->config.rx_ring_num; j++) {
3940 if (sp->config.intr_type == MSI_X) {
3971 struct config_param *config = &sp->config;
3983 for (offset = 1; offset < config->max_mc_addr; offset++) {
4019 struct config_param *config = &sp->config;
4042 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4072 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4074 queue = config->fifo_mapping
4080 if (sp->config.multiq) {
4180 if (sp->config.intr_type == MSI_X)
4213 if (sp->config.napi) {
4237 struct config_param *config = &sp->config;
4257 for (i = 0; i < config->tx_fifo_num; i++)
4670 struct config_param *config;
4679 config = &sp->config;
4698 if (config->napi) {
4714 for (i = 0; i < config->rx_ring_num; i++) {
4729 for (i = 0; i < config->tx_fifo_num; i++)
4738 if (!config->napi) {
4739 for (i = 0; i < config->rx_ring_num; i++) {
4896 struct config_param *config = &sp->config;
4906 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4914 sp->all_multi_pos = config->max_mc_addr - 1;
4982 (config->max_mc_addr - config->max_mac_addr)) {
5002 (config->mc_start_offset + i);
5032 (i + config->mc_start_offset);
5062 struct config_param *config = &sp->config;
5065 for (offset = 0; offset < config->max_mc_addr; offset++) {
5078 struct config_param *config = &sp->config;
5080 for (offset = 0; offset < config->max_mac_addr; offset++)
5085 for (offset = config->mc_start_offset;
5086 offset < config->max_mc_addr; offset++)
5095 struct config_param *config = &sp->config;
5102 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5111 if (i == config->max_mc_addr) {
5149 struct config_param *config = &sp->config;
5152 offset < config->max_mc_addr; offset++) {
5223 struct config_param *config = &sp->config;
5238 for (i = 1; i < config->max_mac_addr; i++) {
5250 if (i == config->max_mac_addr) {
5476 for (i = 0; i < sp->config.rx_ring_num; i++)
5477 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5481 for (i = 0; i < sp->config.tx_fifo_num; i++)
5482 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5484 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
6860 struct config_param *config = &sp->config;
6876 for (i = 0; i < config->rx_ring_num; i++) {
6877 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6912 if (sp->config.intr_type == MSI_X)
6916 sp->config.intr_type = INTA;
6926 if (sp->config.intr_type == MSI_X) {
6977 sp->config.intr_type = INTA;
6990 if (sp->config.intr_type == INTA) {
7004 if (sp->config.intr_type == MSI_X)
7015 struct config_param *config;
7016 config = &sp->config;
7028 if (sp->config.napi) {
7030 if (config->intr_type == MSI_X) {
7031 for (; off < sp->config.rx_ring_num; off++)
7093 struct config_param *config;
7112 config = &sp->config;
7115 for (i = 0; i < config->rx_ring_num; i++) {
7132 if (config->napi) {
7133 if (config->intr_type == MSI_X) {
7134 for (i = 0; i < sp->config.rx_ring_num; i++)
7169 if (sp->config.intr_type == MSI_X)
7182 if (sp->config.intr_type != INTA) {
7194 if (config->napi) {
7195 if (config->intr_type == MSI_X) {
7196 for (i = 0; i < sp->config.rx_ring_num; i++)
7668 struct config_param *config;
7722 sp->config.intr_type = dev_intr_type;
7741 config = &sp->config;
7744 config->napi = napi;
7745 config->tx_steering_type = tx_steering_type;
7748 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7749 config->tx_fifo_num = MAX_TX_FIFOS;
7751 config->tx_fifo_num = tx_fifo_num;
7754 if (config->tx_fifo_num < 5) {
7755 if (config->tx_fifo_num == 1)
7758 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7759 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7770 config->multiq = dev_multiq;
7771 for (i = 0; i < config->tx_fifo_num; i++) {
7772 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7780 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7783 for (i = 0; i < config->tx_fifo_num; i++)
7787 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7788 for (i = 0; i < config->tx_fifo_num; i++) {
7789 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7793 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7798 config->max_txds = MAX_SKB_FRAGS + 2;
7801 config->rx_ring_num = rx_ring_num;
7802 for (i = 0; i < config->rx_ring_num; i++) {
7803 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7816 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7890 if (sp->config.intr_type == MSI_X) {
7891 sp->num_entries = config->rx_ring_num + 1;
7903 sp->config.intr_type = INTA;
7907 if (config->intr_type == MSI_X) {
7908 for (i = 0; i < config->rx_ring_num ; i++) {
7955 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7956 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7957 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7959 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7960 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7961 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7973 (config->intr_type == MSI_X))
7974 sp->num_entries = config->rx_ring_num + 1;
7988 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8042 switch (sp->config.napi) {
8052 sp->config.tx_fifo_num);
8055 sp->config.rx_ring_num);
8057 switch (sp->config.intr_type) {
8065 if (sp->config.multiq) {
8066 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8069 fifo->multiq = config->multiq;
8077 switch (sp->config.tx_steering_type) {
8468 if (sp->config.napi)
8526 * followed by fixups by BIOS, and has its config space