Lines Matching defs:base
412 u8 __iomem *base;
455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
465 dev->base + RXDP);
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
612 tbisr = readl(dev->base + TBISR);
613 tanar = readl(dev->base + TANAR);
614 tanlpar = readl(dev->base + TANLPAR);
622 writel(readl(dev->base + TXCFG)
624 dev->base + TXCFG);
625 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
626 dev->base + RXCFG);
628 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
629 dev->base + GPIOR);
639 writel((readl(dev->base + TXCFG)
641 dev->base + TXCFG);
642 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
643 dev->base + RXCFG);
645 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
646 dev->base + GPIOR);
665 writel(readl(dev->base + TXCFG)
667 dev->base + TXCFG);
668 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
669 dev->base + RXCFG);
671 writel(readl(dev->base + TXCFG)
673 dev->base + TXCFG);
674 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
675 dev->base + RXCFG);
680 writel(new_cfg, dev->base + CFG);
723 writel(0, dev->base + RXDP_HI);
724 writel(dev->rx_info.phy_descs, dev->base + RXDP);
732 writel(0x0001, dev->base + CCSR);
733 writel(0, dev->base + RFCR);
734 writel(0x7fc00000, dev->base + RFCR);
735 writel(0xffc00000, dev->base + RFCR);
754 writel(dev->IMR_cache, dev->base + IMR);
755 writel(1, dev->base + IER);
775 writel(dev->IMR_cache, dev->base + IMR);
783 readl(dev->base + IMR);
786 writel(0, dev->base + RXDP_HI);
787 writel(0, dev->base + RXDP);
831 readl(dev->base + RXDP),
933 writel(ihr, dev->base + IHR);
937 writel(dev->IMR_cache, dev->base + IMR);
950 writel(CR_TXE, dev->base + CR);
1176 u8 __iomem *base = dev->base;
1179 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1180 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1181 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1182 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1183 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1184 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1185 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1186 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1187 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1188 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1189 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1227 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1228 readl(dev->base + TANAR);
1229 tbicr = readl(dev->base + TBICR);
1240 cmd->base.port = PORT_FIBRE;
1248 cmd->base.port = PORT_MII;
1254 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1257 cmd->base.speed = SPEED_1000;
1260 cmd->base.speed = SPEED_100;
1263 cmd->base.speed = SPEED_10;
1266 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1281 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1282 tanar = readl(dev->base + TANAR);
1298 if (cmd->base.duplex != fullduplex) {
1301 if (cmd->base.duplex == DUPLEX_FULL) {
1303 writel(readl(dev->base + TXCFG)
1305 dev->base + TXCFG);
1306 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1307 dev->base + RXCFG);
1309 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1310 dev->base + GPIOR);
1325 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1328 dev->base + TBICR);
1329 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1336 writel(0x00000000, dev->base + TBICR);
1340 cmd->base.autoneg ? "ENABLED" : "DISABLED");
1362 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1375 writel(0, dev->base + IMR);
1376 writel(0, dev->base + IER);
1377 readl(dev->base + IER);
1399 isr = readl(dev->base + ISR);
1426 writel(dev->IMR_cache, dev->base + IMR);
1431 //writel(4, dev->base + IHR);
1448 writel(CR_RXE, dev->base + CR);
1452 txdp = readl(dev->base + TXDP);
1483 writel(dev->IMR_cache, dev->base + IMR);
1497 writel(dev->IMR_cache, dev->base + IMR);
1511 writel(dev->ihr, dev->base + IHR);
1518 writel(which, dev->base + CR);
1521 } while (readl(dev->base + CR) & which);
1570 isr = readl(dev->base + ISR);
1620 writel(0, dev->base + PQCR);
1637 writel(0, dev->base + TXDP_HI);
1638 writel(desc, dev->base + TXDP);
1663 writel(i*2, dev->base + RFCR);
1664 data = readl(dev->base + RFDR);
1675 u8 __iomem *rfcr = dev->base + RFCR;
1710 writel(enable, dev->base + PTSCR);
1713 status = readl(dev->base + PTSCR);
1742 writel(dev->MEAR_cache, dev->base + MEAR);
1743 readl(dev->base + MEAR);
1753 writel(dev->MEAR_cache, dev->base + MEAR);
1754 readl(dev->base + MEAR);
1761 writel(dev->MEAR_cache, dev->base + MEAR);
1762 readl(dev->base + MEAR);
1775 writel(dev->MEAR_cache, dev->base + MEAR);
1776 readl(dev->base + MEAR);
1782 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1784 writel(dev->MEAR_cache, dev->base + MEAR);
1942 dev->base = ioremap(addr, PAGE_SIZE);
1950 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1984 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1995 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2003 dev->CFG_cache = readl(dev->base + CFG);
2039 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2042 writel(readl(dev->base + TANAR)
2044 dev->base + TANAR);
2048 dev->base + TBICR);
2049 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2055 writel(dev->CFG_cache, dev->base + CFG);
2060 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2062 writel(dev->CFG_cache, dev->base + CFG);
2068 if (readl(dev->base + SRR))
2069 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2081 dev->base + TXCFG);
2084 writel(0x000, dev->base + IHR);
2085 writel(0x100, dev->base + IHR);
2086 writel(0x000, dev->base + IHR);
2097 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2100 writel(0, dev->base + PQCR);
2120 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2131 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2134 /* writel(0, dev->base + PCR); */
2137 dev->base + PCR);
2140 writel(0, dev->base + WCSR);
2163 (unsigned)readl(dev->base + SRR) >> 8,
2164 (unsigned)readl(dev->base + SRR) & 0xff,
2188 if (dev->base)
2189 iounmap(dev->base);
2213 iounmap(dev->base);