Lines Matching defs:mgp
180 struct myri10ge_priv *mgp;
369 static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
371 if (mgp->fw_name_allocated)
372 kfree(mgp->fw_name);
373 mgp->fw_name = name;
374 mgp->fw_name_allocated = allocated;
378 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
383 struct mcp_cmd_response *response = mgp->cmd;
384 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
395 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
396 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
446 dev_err(&mgp->pdev->dev,
453 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
465 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
470 ptr = mgp->eeprom_strings;
471 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
476 mgp->mac_addr_string = ptr;
480 mgp->mac_addr[i] =
487 mgp->product_code_string = ptr;
491 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
499 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
508 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
516 mgp->cmd->data = 0;
523 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
524 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
533 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
536 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
538 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
539 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
544 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
547 struct device *dev = &mgp->pdev->dev;
556 strscpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
558 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
559 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
561 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
562 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
563 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
571 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
575 struct device *dev = &mgp->pdev->dev;
582 if (request_firmware(&fw, mgp->fw_name, dev) < 0) {
584 mgp->fw_name);
591 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
607 status = myri10ge_validate_firmware(mgp, hdr);
613 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
617 readb(mgp->sram);
625 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
643 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
646 struct device *dev = &mgp->pdev->dev;
652 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
654 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
666 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
667 status = myri10ge_validate_firmware(mgp, hdr);
673 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
674 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
675 mgp->adopted_rx_filter_bug = 1;
678 mgp->fw_ver_major, mgp->fw_ver_minor,
679 mgp->fw_ver_tiny);
684 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
690 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
691 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
694 mgp->max_tso6 = cmd.data0;
695 mgp->features |= NETIF_F_TSO6;
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
700 dev_err(&mgp->pdev->dev,
705 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
710 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
718 status = myri10ge_load_hotplug_firmware(mgp, &size);
722 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
729 status = myri10ge_adopt_running_firmware(mgp);
731 dev_err(&mgp->pdev->dev,
735 dev_info(&mgp->pdev->dev,
737 if (mgp->tx_boundary == 4096) {
738 dev_warn(&mgp->pdev->dev,
741 dev_warn(&mgp->pdev->dev,
744 dev_warn(&mgp->pdev->dev, "via hotplug\n");
747 set_fw_name(mgp, "adopted", false);
748 mgp->tx_boundary = 2048;
749 myri10ge_dummy_rdma(mgp, 1);
750 status = myri10ge_get_firmware_capabilities(mgp);
755 mgp->cmd->data = 0;
762 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
763 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
778 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
785 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
789 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
790 dev_err(&mgp->pdev->dev, "handoff failed\n");
793 myri10ge_dummy_rdma(mgp, 1);
794 status = myri10ge_get_firmware_capabilities(mgp);
799 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp,
810 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
814 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
820 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
823 netdev_err(mgp->dev, "Failed to set flow control mode\n");
826 mgp->pause = pause;
831 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
837 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
839 netdev_err(mgp->dev, "Failed to set promisc mode\n");
842 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
854 dmatest_bus = dma_map_page(&mgp->pdev->dev, dmatest_page, 0,
856 if (unlikely(dma_mapping_error(&mgp->pdev->dev, dmatest_bus))) {
870 len = mgp->tx_boundary;
875 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
880 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
884 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
889 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
894 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
899 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
903 dma_unmap_page(&mgp->pdev->dev, dmatest_bus, PAGE_SIZE,
908 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
914 static int myri10ge_reset(struct myri10ge_priv *mgp)
927 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
929 dev_err(&mgp->pdev->dev, "failed reset\n");
933 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
941 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
945 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
947 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
960 if (mgp->num_slices > 1) {
963 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
966 dev_err(&mgp->pdev->dev,
975 cmd.data0 = mgp->num_slices;
977 if (mgp->dev->real_num_tx_queues > 1)
979 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
985 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
986 netif_set_real_num_tx_queues(mgp->dev, 1);
987 cmd.data0 = mgp->num_slices;
989 status = myri10ge_send_cmd(mgp,
995 dev_err(&mgp->pdev->dev,
1001 for (i = 0; i < mgp->num_slices; i++) {
1002 ss = &mgp->ss[i];
1006 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1011 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1012 for (i = 0; i < mgp->num_slices; i++) {
1013 ss = &mgp->ss[i];
1015 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1017 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1019 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1022 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1023 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1025 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1028 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1031 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1033 for (i = 0; i < mgp->num_slices; i++) {
1034 ss = &mgp->ss[i];
1037 (mgp->sram + dca_tag_off + 4 * i);
1046 mgp->link_changes = 0;
1047 for (i = 0; i < mgp->num_slices; i++) {
1048 ss = &mgp->ss[i];
1063 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1064 myri10ge_change_pause(mgp, mgp->pause);
1065 myri10ge_set_multicast_list(mgp->dev);
1099 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
1107 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1110 struct pci_dev *pdev = mgp->pdev;
1112 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1125 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
1126 mgp->dca_enabled = 1;
1127 for (i = 0; i < mgp->num_slices; i++) {
1128 mgp->ss[i].cpu = -1;
1129 mgp->ss[i].cached_dca_tag = -1;
1130 myri10ge_update_dca(&mgp->ss[i]);
1134 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1136 struct pci_dev *pdev = mgp->pdev;
1138 if (!mgp->dca_enabled)
1140 mgp->dca_enabled = 0;
1141 if (mgp->relaxed_order)
1148 struct myri10ge_priv *mgp;
1151 mgp = dev_get_drvdata(dev);
1155 myri10ge_setup_dca(mgp);
1157 myri10ge_teardown_dca(mgp);
1180 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1210 bus = dma_map_page(&mgp->pdev->dev, page, 0,
1213 if (unlikely(dma_mapping_error(&mgp->pdev->dev, bus))) {
1309 struct myri10ge_priv *mgp = ss->mgp;
1314 struct pci_dev *pdev = mgp->pdev;
1315 struct net_device *dev = mgp->dev;
1318 if (len <= mgp->small_bytes) {
1320 bytes = mgp->small_bytes;
1323 bytes = mgp->big_bytes;
1368 myri10ge_vlan_rx(mgp->dev, va, skb);
1369 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1379 struct pci_dev *pdev = ss->mgp->pdev;
1416 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1426 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1439 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
1449 struct myri10ge_priv *mgp = ss->mgp;
1467 idx = cnt & (mgp->max_intr_slots - 1);
1477 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1478 mgp->small_bytes + MXGEFW_PAD, 0);
1480 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1485 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1487 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1491 if (mgp->link_state != link_up) {
1492 mgp->link_state = link_up;
1494 if (mgp->link_state == MXGEFW_LINK_UP) {
1495 netif_info(mgp, link, mgp->dev, "link up\n");
1496 netif_carrier_on(mgp->dev);
1497 mgp->link_changes++;
1499 netif_info(mgp, link, mgp->dev, "link %s\n",
1503 netif_carrier_off(mgp->dev);
1504 mgp->link_changes++;
1507 if (mgp->rdma_tags_available !=
1509 mgp->rdma_tags_available =
1511 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1512 mgp->rdma_tags_available);
1514 mgp->down_cnt += stats->link_down;
1516 wake_up(&mgp->down_wq);
1527 if (ss->mgp->dca_enabled)
1543 struct myri10ge_priv *mgp = ss->mgp;
1551 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1565 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1566 put_be32(0, mgp->irq_deassert);
1582 netdev_warn(mgp->dev, "irq stuck?\n");
1584 schedule_work(&mgp->watchdog_work);
1593 if (ss == mgp->ss)
1594 myri10ge_check_statblock(mgp);
1604 struct myri10ge_priv *mgp = netdev_priv(netdev);
1618 ptr = mgp->product_code_string;
1627 mgp->product_code_string);
1648 struct myri10ge_priv *mgp = netdev_priv(netdev);
1652 strscpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1653 strscpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1661 struct myri10ge_priv *mgp = netdev_priv(netdev);
1663 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1672 struct myri10ge_priv *mgp = netdev_priv(netdev);
1674 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1675 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1683 struct myri10ge_priv *mgp = netdev_priv(netdev);
1686 pause->rx_pause = mgp->pause;
1687 pause->tx_pause = mgp->pause;
1694 struct myri10ge_priv *mgp = netdev_priv(netdev);
1696 if (pause->tx_pause != mgp->pause)
1697 return myri10ge_change_pause(mgp, pause->tx_pause);
1698 if (pause->rx_pause != mgp->pause)
1699 return myri10ge_change_pause(mgp, pause->rx_pause);
1711 struct myri10ge_priv *mgp = netdev_priv(netdev);
1713 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1714 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1716 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1759 struct myri10ge_priv *mgp = netdev_priv(netdev);
1767 for (i = 0; i < mgp->num_slices; i++) {
1778 struct myri10ge_priv *mgp = netdev_priv(netdev);
1783 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1793 struct myri10ge_priv *mgp = netdev_priv(netdev);
1805 data[i++] = (unsigned int)mgp->tx_boundary;
1806 data[i++] = (unsigned int)mgp->pdev->irq;
1807 data[i++] = (unsigned int)mgp->msi_enabled;
1808 data[i++] = (unsigned int)mgp->msix_enabled;
1809 data[i++] = (unsigned int)mgp->read_dma;
1810 data[i++] = (unsigned int)mgp->write_dma;
1811 data[i++] = (unsigned int)mgp->read_write_dma;
1812 data[i++] = (unsigned int)mgp->serial_number;
1813 data[i++] = (unsigned int)mgp->watchdog_resets;
1815 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1816 data[i++] = (unsigned int)(mgp->dca_enabled);
1818 data[i++] = (unsigned int)mgp->link_changes;
1821 ss = &mgp->ss[0];
1837 for (slice = 0; slice < mgp->num_slices; slice++) {
1838 ss = &mgp->ss[slice];
1854 struct myri10ge_priv *mgp = netdev_priv(netdev);
1855 mgp->msg_enable = value;
1860 struct myri10ge_priv *mgp = netdev_priv(netdev);
1861 return mgp->msg_enable;
1869 static int myri10ge_led(struct myri10ge_priv *mgp, int on)
1872 struct device *dev = &mgp->pdev->dev;
1877 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
1878 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
1883 hdr_len = swab32(readl(mgp->sram + hdr_off +
1891 pattern = swab32(readl(mgp->sram + pattern_off + 4));
1892 writel(swab32(pattern), mgp->sram + pattern_off);
1899 struct myri10ge_priv *mgp = netdev_priv(netdev);
1904 rc = myri10ge_led(mgp, 1);
1908 rc = myri10ge_led(mgp, 0);
1938 struct myri10ge_priv *mgp = ss->mgp;
1940 struct net_device *dev = mgp->dev;
1947 slice = ss - mgp->ss;
1949 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1952 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
2013 if (mgp->small_bytes == 0) {
2016 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2017 mgp->small_bytes + MXGEFW_PAD, 0);
2026 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2038 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2039 mgp->big_bytes);
2044 if (mgp->small_bytes == 0)
2048 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2049 mgp->small_bytes + MXGEFW_PAD);
2078 struct myri10ge_priv *mgp = ss->mgp;
2091 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2092 mgp->big_bytes);
2096 if (mgp->small_bytes == 0)
2103 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2104 mgp->small_bytes + MXGEFW_PAD);
2121 dma_unmap_single(&mgp->pdev->dev,
2127 dma_unmap_page(&mgp->pdev->dev,
2148 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2150 struct pci_dev *pdev = mgp->pdev;
2152 struct net_device *netdev = mgp->dev;
2156 mgp->msi_enabled = 0;
2157 mgp->msix_enabled = 0;
2160 if (mgp->num_slices > 1) {
2161 status = pci_enable_msix_range(pdev, mgp->msix_vectors,
2162 mgp->num_slices, mgp->num_slices);
2168 mgp->msix_enabled = 1;
2170 if (mgp->msix_enabled == 0) {
2177 mgp->msi_enabled = 1;
2181 if (mgp->msix_enabled) {
2182 for (i = 0; i < mgp->num_slices; i++) {
2183 ss = &mgp->ss[i];
2186 status = request_irq(mgp->msix_vectors[i].vector,
2194 free_irq(mgp->msix_vectors[i].vector,
2195 &mgp->ss[i]);
2204 mgp->dev->name, &mgp->ss[0]);
2207 if (mgp->msi_enabled)
2214 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2216 struct pci_dev *pdev = mgp->pdev;
2219 if (mgp->msix_enabled) {
2220 for (i = 0; i < mgp->num_slices; i++)
2221 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2223 free_irq(pdev->irq, &mgp->ss[0]);
2225 if (mgp->msi_enabled)
2227 if (mgp->msix_enabled)
2231 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2237 ss = &mgp->ss[slice];
2239 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2241 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2244 (mgp->sram + cmd.data0);
2247 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2250 (mgp->sram + cmd.data0);
2253 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2255 (mgp->sram + cmd.data0);
2258 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2260 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2265 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2271 ss = &mgp->ss[slice];
2275 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2283 status = myri10ge_send_cmd(mgp,
2287 mgp->fw_multicast_support = 0;
2289 mgp->fw_multicast_support = 1;
2297 struct myri10ge_priv *mgp = netdev_priv(dev);
2302 if (mgp->running != MYRI10GE_ETH_STOPPED)
2305 mgp->running = MYRI10GE_ETH_STARTING;
2306 status = myri10ge_reset(mgp);
2312 if (mgp->num_slices > 1) {
2313 cmd.data0 = mgp->num_slices;
2315 if (mgp->dev->real_num_tx_queues > 1)
2317 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2324 cmd.data0 = mgp->num_slices;
2325 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2328 status |= myri10ge_send_cmd(mgp,
2337 itable = mgp->sram + cmd.data0;
2338 for (i = 0; i < mgp->num_slices; i++)
2343 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2351 status = myri10ge_request_irq(mgp);
2363 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2368 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2372 mgp->small_bytes = myri10ge_small_bytes;
2382 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2385 mgp->big_bytes = big_pow2;
2389 for (slice = 0; slice < mgp->num_slices; slice++) {
2390 ss = &mgp->ss[slice];
2392 status = myri10ge_get_txrx(mgp, slice);
2404 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2405 status = myri10ge_set_stats(mgp, slice);
2417 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2418 cmd.data0 = mgp->small_bytes;
2420 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2423 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2435 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2441 mgp->link_state = ~0U;
2442 mgp->rdma_tags_available = 15;
2444 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2450 mgp->running = MYRI10GE_ETH_RUNNING;
2451 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2452 add_timer(&mgp->watchdog_timer);
2460 napi_disable(&mgp->ss[slice].napi);
2462 for (i = 0; i < mgp->num_slices; i++)
2463 myri10ge_free_rings(&mgp->ss[i]);
2465 myri10ge_free_irq(mgp);
2468 mgp->running = MYRI10GE_ETH_STOPPED;
2474 struct myri10ge_priv *mgp = netdev_priv(dev);
2479 if (mgp->running != MYRI10GE_ETH_RUNNING)
2482 if (mgp->ss[0].tx.req_bytes == NULL)
2485 del_timer_sync(&mgp->watchdog_timer);
2486 mgp->running = MYRI10GE_ETH_STOPPING;
2487 for (i = 0; i < mgp->num_slices; i++)
2488 napi_disable(&mgp->ss[i].napi);
2493 if (mgp->rebooted == 0) {
2494 old_down_cnt = mgp->down_cnt;
2497 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2501 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2503 if (old_down_cnt == mgp->down_cnt)
2507 myri10ge_free_irq(mgp);
2508 for (i = 0; i < mgp->num_slices; i++)
2509 myri10ge_free_rings(&mgp->ss[i]);
2511 mgp->running = MYRI10GE_ETH_STOPPED;
2582 static void myri10ge_unmap_tx_dma(struct myri10ge_priv *mgp,
2595 dma_unmap_single(&mgp->pdev->dev,
2600 dma_unmap_page(&mgp->pdev->dev,
2624 struct myri10ge_priv *mgp = netdev_priv(dev);
2640 ss = &mgp->ss[queue];
2641 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2703 if (unlikely(-cum_len > mgp->max_tso6))
2726 bus = dma_map_single(&mgp->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2727 if (unlikely(dma_mapping_error(&mgp->pdev->dev, bus)))
2760 * do not cross mgp->tx_boundary */
2771 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2833 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
2835 if (unlikely(dma_mapping_error(&mgp->pdev->dev, bus))) {
2836 myri10ge_unmap_tx_dma(mgp, tx, idx);
2856 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2869 myri10ge_unmap_tx_dma(mgp, tx, idx);
2872 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2893 struct myri10ge_priv *mgp = netdev_priv(dev);
2917 ss = &mgp->ss[skb_get_queue_mapping(skb)];
2926 const struct myri10ge_priv *mgp = netdev_priv(dev);
2930 for (i = 0; i < mgp->num_slices; i++) {
2931 slice_stats = &mgp->ss[i].stats;
2943 struct myri10ge_priv *mgp = netdev_priv(dev);
2951 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2954 if (!mgp->fw_multicast_support)
2959 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2966 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2973 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2986 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2996 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3012 struct myri10ge_priv *mgp = netdev_priv(dev);
3018 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3032 struct myri10ge_priv *mgp = netdev_priv(dev);
3035 if (mgp->running) {
3053 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3055 struct pci_dev *bridge = mgp->pdev->bus->self;
3056 struct device *dev = &mgp->pdev->dev;
3134 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3136 struct pci_dev *pdev = mgp->pdev;
3140 mgp->tx_boundary = 4096;
3152 mgp->tx_boundary = 2048;
3158 set_fw_name(mgp, myri10ge_fw_aligned, false);
3159 status = myri10ge_load_firmware(mgp, 1);
3167 myri10ge_enable_ecrc(mgp);
3174 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3185 mgp->tx_boundary = 2048;
3186 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3189 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3197 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
3204 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3206 mgp->tx_boundary = 4096;
3207 set_fw_name(mgp, myri10ge_fw_aligned, false);
3209 myri10ge_firmware_probe(mgp);
3213 dev_info(&mgp->pdev->dev,
3215 mgp->tx_boundary = 4096;
3216 set_fw_name(mgp, myri10ge_fw_aligned, false);
3218 dev_info(&mgp->pdev->dev,
3220 mgp->tx_boundary = 2048;
3221 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3230 set_fw_name(mgp, fw_name, true);
3235 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3236 myri10ge_fw_names[mgp->board_number] != NULL &&
3237 strlen(myri10ge_fw_names[mgp->board_number])) {
3238 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
3242 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3243 mgp->fw_name);
3268 struct myri10ge_priv *mgp;
3271 mgp = dev_get_drvdata(dev);
3272 if (mgp == NULL)
3274 netdev = mgp->dev;
3283 myri10ge_dummy_rdma(mgp, 0);
3291 struct myri10ge_priv *mgp;
3296 mgp = pci_get_drvdata(pdev);
3297 if (mgp == NULL)
3299 netdev = mgp->dev;
3301 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3303 netdev_err(mgp->dev, "device disappeared!\n");
3307 myri10ge_reset(mgp);
3308 myri10ge_dummy_rdma(mgp, 1);
3326 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3328 struct pci_dev *pdev = mgp->pdev;
3329 int vs = mgp->vendor_specific_offset;
3345 struct myri10ge_priv *mgp = ss->mgp;
3346 int slice = ss - mgp->ss;
3352 if (rx_pause_cnt != mgp->watchdog_pause) {
3354 netdev_warn(mgp->dev, "slice %d: TX paused, "
3357 netdev_warn(mgp->dev,
3362 (int)ntohl(mgp->ss[slice].fw_stats->
3383 struct myri10ge_priv *mgp =
3393 mgp->watchdog_resets++;
3394 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3400 reboot = myri10ge_read_reboot(mgp);
3401 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3406 mgp->rebooted = 1;
3408 myri10ge_close(mgp->dev);
3410 mgp->rebooted = 0;
3418 pci_restore_state(mgp->pdev);
3421 pci_save_state(mgp->pdev);
3428 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3430 netdev_err(mgp->dev, "device disappeared!\n");
3436 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3437 for (i = 0; i < mgp->num_slices; i++) {
3438 ss = mgp->ss;
3447 netdev_dbg(mgp->dev, "not resetting\n");
3451 netdev_err(mgp->dev, "device timeout, resetting\n");
3456 myri10ge_close(mgp->dev);
3458 status = myri10ge_load_firmware(mgp, 1);
3460 netdev_err(mgp->dev, "failed to load firmware\n");
3462 myri10ge_open(mgp->dev);
3475 struct myri10ge_priv *mgp;
3481 mgp = from_timer(mgp, t, watchdog_timer);
3483 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3486 i < mgp->num_slices && reset_needed == 0; ++i) {
3488 ss = &mgp->ss[i];
3490 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3491 mgp->small_bytes + MXGEFW_PAD,
3498 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3499 mgp->big_bytes, 1);
3511 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3516 mgp->watchdog_pause = rx_pause_cnt;
3519 schedule_work(&mgp->watchdog_work);
3522 mod_timer(&mgp->watchdog_timer,
3527 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3530 struct pci_dev *pdev = mgp->pdev;
3534 if (mgp->ss == NULL)
3537 for (i = 0; i < mgp->num_slices; i++) {
3538 ss = &mgp->ss[i];
3540 bytes = mgp->max_intr_slots *
3556 kfree(mgp->ss);
3557 mgp->ss = NULL;
3560 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3563 struct pci_dev *pdev = mgp->pdev;
3567 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3568 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3569 if (mgp->ss == NULL) {
3573 for (i = 0; i < mgp->num_slices; i++) {
3574 ss = &mgp->ss[i];
3575 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3587 ss->mgp = mgp;
3588 ss->dev = mgp->dev;
3594 myri10ge_free_slices(mgp);
3604 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3607 struct pci_dev *pdev = mgp->pdev;
3612 mgp->num_slices = 1;
3620 old_fw = mgp->fw_name;
3621 old_allocated = mgp->fw_name_allocated;
3623 mgp->fw_name_allocated = false;
3626 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3628 set_fw_name(mgp, myri10ge_fw_name, false);
3630 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
3632 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
3633 status = myri10ge_load_firmware(mgp, 0);
3643 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3645 dev_err(&mgp->pdev->dev, "failed reset\n");
3649 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3652 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3653 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3655 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3660 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3664 mgp->num_slices = cmd.data0;
3677 if (mgp->num_slices > myri10ge_max_slices)
3678 mgp->num_slices = myri10ge_max_slices;
3684 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3686 if (mgp->msix_vectors == NULL)
3688 for (i = 0; i < mgp->num_slices; i++) {
3689 mgp->msix_vectors[i].entry = i;
3692 while (mgp->num_slices > 1) {
3693 mgp->num_slices = rounddown_pow_of_two(mgp->num_slices);
3694 if (mgp->num_slices == 1)
3697 mgp->msix_vectors,
3698 mgp->num_slices,
3699 mgp->num_slices);
3705 if (status == mgp->num_slices) {
3710 mgp->num_slices = status;
3715 if (mgp->msix_vectors != NULL) {
3716 kfree(mgp->msix_vectors);
3717 mgp->msix_vectors = NULL;
3721 mgp->num_slices = 1;
3722 set_fw_name(mgp, old_fw, old_allocated);
3723 myri10ge_load_firmware(mgp, 0);
3740 struct myri10ge_priv *mgp;
3746 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3752 mgp = netdev_priv(netdev);
3753 mgp->dev = netdev;
3754 mgp->pdev = pdev;
3755 mgp->pause = myri10ge_flow_control;
3756 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3757 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3758 mgp->board_number = board_number;
3759 init_waitqueue_head(&mgp->down_wq);
3769 mgp->vendor_specific_offset
3787 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3788 &mgp->cmd_bus, GFP_KERNEL);
3789 if (!mgp->cmd) {
3794 mgp->board_span = pci_resource_len(pdev, 0);
3795 mgp->iomem_base = pci_resource_start(pdev, 0);
3796 mgp->wc_cookie = arch_phys_wc_add(mgp->iomem_base, mgp->board_span);
3797 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3798 if (mgp->sram == NULL) {
3800 mgp->board_span, mgp->iomem_base);
3805 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3807 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
3808 if (mgp->sram_size > mgp->board_span ||
3809 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3812 mgp->sram_size, mgp->board_span);
3816 memcpy_fromio(mgp->eeprom_strings,
3817 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3818 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3819 status = myri10ge_read_mac_addr(mgp);
3823 eth_hw_addr_set(netdev, mgp->mac_addr);
3825 myri10ge_select_firmware(mgp);
3827 status = myri10ge_load_firmware(mgp, 1);
3832 myri10ge_probe_slices(mgp);
3833 status = myri10ge_alloc_slices(mgp);
3838 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3839 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
3840 status = myri10ge_reset(mgp);
3846 myri10ge_setup_dca(mgp);
3848 pci_set_drvdata(pdev, mgp);
3862 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
3869 netdev->vlan_features |= mgp->features;
3870 if (mgp->fw_ver_tiny < 37)
3872 if (mgp->fw_ver_tiny < 32)
3877 status = myri10ge_request_irq(mgp);
3880 myri10ge_free_irq(mgp);
3887 timer_setup(&mgp->watchdog_timer, myri10ge_watchdog_timer, 0);
3890 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3896 if (mgp->msix_enabled)
3898 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3899 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
3902 mgp->msi_enabled ? "MSI" : "xPIC",
3903 pdev->irq, mgp->tx_boundary, mgp->fw_name,
3904 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
3913 myri10ge_free_slices(mgp);
3916 kfree(mgp->msix_vectors);
3917 myri10ge_dummy_rdma(mgp, 0);
3920 if (mgp->mac_addr_string != NULL)
3923 mgp->mac_addr_string, mgp->serial_number);
3924 iounmap(mgp->sram);
3927 arch_phys_wc_del(mgp->wc_cookie);
3928 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3929 mgp->cmd, mgp->cmd_bus);
3935 set_fw_name(mgp, NULL, false);
3949 struct myri10ge_priv *mgp;
3952 mgp = pci_get_drvdata(pdev);
3953 if (mgp == NULL)
3956 cancel_work_sync(&mgp->watchdog_work);
3957 netdev = mgp->dev;
3961 myri10ge_teardown_dca(mgp);
3963 myri10ge_dummy_rdma(mgp, 0);
3968 iounmap(mgp->sram);
3969 arch_phys_wc_del(mgp->wc_cookie);
3970 myri10ge_free_slices(mgp);
3971 kfree(mgp->msix_vectors);
3972 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3973 mgp->cmd, mgp->cmd_bus);
3975 set_fw_name(mgp, NULL, false);