Lines Matching refs:val
34 static enum ethtool_mm_verify_status ocelot_mm_verify_status(u32 val)
36 switch (DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(val)) {
56 u32 val = 0;
67 val = mm->preemptible_tcs;
75 mm->active_preemptible_tcs = val;
85 ocelot_rmw_rix(ocelot, QSYS_PREEMPTION_CFG_P_QUEUES(val),
110 u32 val, ack = 0;
115 val = ocelot_port_readl(ocelot_port, DEV_MM_STATUS);
117 verify_status = ocelot_mm_verify_status(val);
125 if (val & DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY) {
126 mm->tx_active = !!(val & DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS);
135 if (val & DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY) {
143 if (val & DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY) {
239 u32 val, add_frag_size;
248 val = ocelot_port_readl(ocelot_port, DEV_MM_ENABLE_CONFIG);
249 state->pmac_enabled = !!(val & DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA);
250 state->tx_enabled = !!(val & DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA);
252 val = ocelot_port_readl(ocelot_port, DEV_MM_VERIF_CONFIG);
253 state->verify_enabled = !(val & DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS);
254 state->verify_time = DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(val);
257 val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port);
258 add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val);
287 u32 val;
295 val = ocelot_port_readl(ocelot_port, DEV_MM_STATUS);
296 mm->verify_status = ocelot_mm_verify_status(val);