Lines Matching refs:rx_cfg
1167 * @rx_cfg: Cached receive control settings.
1207 u32 rx_cfg;
2837 u32 rx_cfg;
2840 rx_cfg = hw->rx_cfg;
2843 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
2845 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
2851 if (rx_cfg != hw->rx_cfg)
2852 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3405 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3407 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3410 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3413 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3415 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3514 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3538 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3832 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3834 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
3853 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3855 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4642 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
4838 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5048 hw->rx_cfg |= DMA_RX_ERROR;
5051 hw->rx_cfg &= ~DMA_RX_ERROR;
5955 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6212 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6214 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6217 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);