Lines Matching defs:reg
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1049 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1062 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1078 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1085 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1091 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1097 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1105 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
1135 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1162 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1170 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1184 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1190 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1196 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1202 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1208 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1235 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1241 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1263 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1269 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1313 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1322 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1334 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1394 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1400 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1433 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1440 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1446 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1453 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1508 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1515 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1534 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1559 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1567 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1583 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1592 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1598 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1604 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1612 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1620 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1628 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
1639 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
1648 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
1708 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1715 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1723 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1732 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1740 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1752 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1768 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1782 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1810 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1818 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1848 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1854 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1866 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
1876 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
1884 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1893 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1901 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1910 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1919 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1930 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
1939 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
1948 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
1958 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
1998 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
2004 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
2011 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
2018 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
2055 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12);
2063 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1);
2092 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
2103 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
2113 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
2124 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
2134 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
2145 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
2155 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2187 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
2196 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2221 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
2228 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
2234 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);
2260 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2267 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2276 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
2284 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
2290 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2296 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2326 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2332 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2338 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2346 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2353 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2404 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2410 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2418 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2426 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2434 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2442 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2450 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2458 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2466 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2474 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2509 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2534 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2544 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2550 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2558 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2565 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2593 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2600 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2609 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2643 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2650 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2658 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2664 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2711 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2718 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2729 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2739 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2746 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2754 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2765 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2806 MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);
2812 MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);
2818 MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);
2824 MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);
2830 MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);
2836 MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);
2843 MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);
2851 MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);
2857 MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);
2879 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2885 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2920 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2926 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2932 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2938 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2945 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2951 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2985 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2994 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
3002 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
3011 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
3048 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
3055 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
3082 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
3089 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
3112 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
3117 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
3126 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
3132 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
3141 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
3150 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
3157 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
3187 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
3194 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
3206 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
3215 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
3221 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
3228 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
3235 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
3241 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
3247 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
3255 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3300 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3316 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3340 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3358 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3366 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3372 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3380 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3387 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3394 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3405 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3412 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3424 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3432 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3445 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3455 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3462 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3503 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3509 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3515 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3524 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3532 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3558 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3564 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3570 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3577 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3586 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3595 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3603 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3648 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3656 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3665 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3674 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3715 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3721 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3728 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3735 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3772 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3783 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3813 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3819 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3825 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3832 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3840 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3853 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3866 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3879 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3888 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3898 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3906 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3922 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3928 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
3976 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
3983 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3989 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3999 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
4025 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
4041 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
4047 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
4055 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
4064 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
4076 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
4092 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
4103 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
4112 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
4123 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
4132 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
4141 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
4151 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
4161 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
4204 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
4210 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
4216 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
4245 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
4251 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4260 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4268 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4277 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4285 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4294 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4331 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4337 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4366 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4374 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4381 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4417 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4424 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4455 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4463 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4471 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4478 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4486 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4492 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4500 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4510 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4520 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4554 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4560 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4570 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4576 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4585 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
4591 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4598 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4619 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4628 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4636 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4645 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4675 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4681 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4693 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4705 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4725 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4757 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4763 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4769 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4775 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4781 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4799 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4868 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4874 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
4881 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4907 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4913 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
4924 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4934 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4940 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4947 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4956 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4984 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
4992 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
5001 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
5010 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
5022 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
5029 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
5036 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
5044 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
5052 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
5064 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
5072 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
5080 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
5089 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
5126 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
5132 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
5140 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
5171 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
5179 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
5187 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
5197 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
5204 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5210 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5216 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5222 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5228 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5234 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5240 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5246 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5252 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5258 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5264 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5270 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5276 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5282 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5288 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5294 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5300 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5306 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5312 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5320 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5326 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5332 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5340 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5346 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5352 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5358 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5364 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5370 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5376 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5382 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5388 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5394 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5400 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5406 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5412 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5420 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5426 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5432 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5438 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5446 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5454 MLXSW_ITEM64(reg, ppcnt, ingress_general,
5460 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5466 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5472 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5478 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5484 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5490 MLXSW_ITEM64(reg, ppcnt, egress_general,
5496 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5502 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5508 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5514 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5520 MLXSW_ITEM64(reg, ppcnt, egress_sll,
5528 MLXSW_ITEM64(reg, ppcnt, rx_octets,
5534 MLXSW_ITEM64(reg, ppcnt, rx_frames,
5540 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5546 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5552 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5558 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5564 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5570 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5576 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5587 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5595 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5603 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5609 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc,
5650 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5656 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
5662 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5669 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5676 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5683 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5692 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5699 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5733 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
5740 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5748 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5758 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5767 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5774 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5785 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5797 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5843 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5849 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
5856 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5881 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
5887 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5893 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5911 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
5919 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5927 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
5939 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
5961 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
5972 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5999 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4);
6005 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8);
6011 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4);
6017 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4);
6027 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4);
6035 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
6061 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);
6068 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);
6076 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);
6085 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);
6097 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2);
6127 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
6133 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
6146 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
6152 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
6167 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12);
6177 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
6188 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
6194 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
6218 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8);
6224 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4);
6230 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
6240 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
6251 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16);
6273 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12);
6279 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8);
6285 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4);
6291 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4);
6321 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4);
6327 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
6350 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5);
6372 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
6380 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
6427 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
6438 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6446 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6459 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6465 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6480 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6488 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6500 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6547 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6575 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6581 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6590 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6606 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6635 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6641 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6648 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6658 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6669 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6685 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6708 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6715 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6722 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6728 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6734 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6751 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6767 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6773 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6782 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6791 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6799 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6807 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6816 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6822 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6828 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6834 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6840 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4);
6847 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6854 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6861 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6869 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12);
6878 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);
6889 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6898 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6905 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6915 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);
6921 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6937 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6952 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6962 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6970 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6977 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6983 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6984 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6991 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
7010 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
7016 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
7022 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
7028 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
7168 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
7179 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
7188 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
7233 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
7247 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
7254 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
7286 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
7295 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
7301 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
7315 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
7321 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
7334 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
7340 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
7354 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
7361 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
7368 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
7383 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
7389 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
7457 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
7464 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
7487 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
7505 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7520 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7526 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7532 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7538 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7545 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7552 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7559 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7565 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7571 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7578 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7585 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7616 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7622 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7628 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7635 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7641 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7671 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7683 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7691 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7723 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7729 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7741 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7749 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7789 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7795 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7803 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7829 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7862 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7871 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7878 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7891 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7899 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7909 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7910 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7923 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7933 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
7950 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7965 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7973 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7980 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7990 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7997 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
8009 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
8017 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
8113 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
8144 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
8153 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
8159 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
8165 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
8166 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
8179 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
8193 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
8199 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
8205 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
8211 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
8263 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
8270 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
8276 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
8282 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
8288 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
8294 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
8341 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
8351 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
8361 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
8368 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
8381 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
8388 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
8409 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
8419 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
8429 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8436 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8443 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8453 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
8460 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
8467 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
8505 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8512 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8519 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8527 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8547 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8561 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8572 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8579 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8588 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8595 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8656 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
8662 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16);
8692 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8701 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8707 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8714 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8742 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8748 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8755 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8761 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8770 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8780 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8788 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8820 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8826 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8832 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8856 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8891 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8898 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8933 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
8956 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
8966 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
8983 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
8990 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
8996 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
9002 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
9013 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
9019 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
9025 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
9026 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
9033 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
9034 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
9040 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
9041 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
9048 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
9049 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
9062 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
9139 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4);
9146 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16);
9154 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1,
9162 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12,
9196 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9204 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9212 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9245 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9252 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9276 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9282 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9305 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9311 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9317 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9354 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9382 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9399 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);
9409 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9423 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9430 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9436 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9442 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9449 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9465 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9473 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9480 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9488 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9545 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9565 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);
9572 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9581 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9588 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9596 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
9642 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
9648 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4);
9668 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
9674 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
9680 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
9686 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
9692 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
9698 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
9738 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128);
9775 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
9782 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
9788 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
9794 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
9805 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
9815 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
9839 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
9845 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
9851 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
9861 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
9875 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
9881 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
9887 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
9902 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
9908 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
9914 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
9920 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
9921 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
9927 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
9928 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
9999 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4);
10010 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
10017 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10023 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
10034 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10062 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
10068 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1);
10074 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1);
10082 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
10087 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
10092 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
10097 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
10131 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10152 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
10162 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10169 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10194 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8);
10200 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4);
10211 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16);
10235 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10246 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10254 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10264 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10297 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10307 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10315 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10324 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);
10334 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);
10363 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10373 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10380 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10387 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10393 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10400 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10406 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10454 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10461 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10467 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10474 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10480 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10488 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10529 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10533 * accordance to log_mcda_word_size in MCQI reg.
10536 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10542 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10548 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10582 MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);
10598 MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \
10651 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12);
10657 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10666 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10689 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10695 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
10708 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
10714 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
10720 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
10748 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
10756 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
10764 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
10790 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
10799 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
10807 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
10834 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
10840 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
10850 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
10876 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12);
10893 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
10901 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
10930 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
10939 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
10971 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12);
10982 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
10988 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
10995 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
11002 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
11010 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
11018 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
11028 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
11036 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
11076 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
11084 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
11109 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1);
11117 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12);
11124 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1);
11133 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16);
11142 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16);
11169 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
11174 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
11195 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4);
11200 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11206 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11212 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11218 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);
11224 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);
11230 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11271 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
11277 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
11290 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);
11296 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
11303 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
11325 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);
11336 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4);
11344 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);
11392 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4);
11398 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8);
11404 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8);
11410 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8);
11420 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8);
11430 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2);
11435 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16);
11449 const struct mlxsw_reg_info *reg,
11452 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
11461 mlxsw_reg_mddt_register_id_set(payload, reg->id);
11484 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);
11498 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8);
11504 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);
11512 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8);
11519 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8);
11526 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1);
11532 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);
11539 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);
11552 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);
11558 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);
11565 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);
11572 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);
11577 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8);
11619 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1);
11625 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8);
11631 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16);
11637 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16);
11643 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16);
11675 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10,
11704 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4);
11710 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1);
11716 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
11739 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11754 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8);
11772 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11782 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11788 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11799 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11805 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11811 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32);
11818 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1);
11824 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4);
11830 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64);
11837 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1);
11843 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16);
11849 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32);
11850 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32);
11851 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32);
11852 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32);
11853 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32);
11859 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
11865 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
11872 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
11879 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
11885 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
11891 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
11897 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18);
11904 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
11910 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
11934 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
11940 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
11946 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
11952 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
11968 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
11985 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
11991 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
11998 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
12015 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
12022 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
12032 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
12042 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
12049 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
12056 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
12063 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
12069 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
12076 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
12116 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
12122 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
12129 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
12135 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
12141 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
12148 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
12154 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
12161 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
12196 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
12218 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12);
12224 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
12247 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
12253 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
12277 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
12283 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
12290 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
12298 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
12305 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
12333 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
12339 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
12345 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
12371 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
12378 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
12401 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
12407 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
12431 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
12437 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
12444 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
12452 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
12459 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
12486 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1);
12498 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
12504 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
12510 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
12517 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
12528 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
12560 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
12570 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
12576 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
12582 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
12592 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
12606 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
12612 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
12646 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
12652 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
12658 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
12664 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
12672 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12679 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
12685 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
12698 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
12735 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
12741 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
12754 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
12760 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
12796 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12806 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
12815 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12825 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12834 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12844 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12856 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12864 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12895 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
12903 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
13092 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
13098 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
13109 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
13119 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);