Lines Matching defs:priority
886 * untagged VLAN membership (u bit is set) will be tagged with priority tag
1002 * When set, priority tagged frames on the ingress are allowed (default).
3121 * Note: priority does not have to be unique per rule.
3122 * Within a region, higher priority should have lower offset (no limitation
3126 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
3163 u16 offset, u32 priority)
3169 mlxsw_reg_ptce2_priority_set(payload, priority);
3366 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3466 u32 priority,
3476 mlxsw_reg_ptce3_priority_set(payload, priority);
3758 * This register controls the port policy to calculate the switch priority and
3962 * Configures the mapping between the packet switch priority and the
3986 * Switch priority.
4137 * 0 - Strict priority
4148 * transmission selection algorithm is strict priority.
5025 * Bit per priority indicating if Tx flow control policy should be
5032 * Bit per priority indicating if Rx flow control policy should be
5055 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
5056 * 0 - Never generate priority Pause frames on the specified priority
5058 * 1 - Generate priority Pause frames according to Rx buffer threshold on
5059 * the specified priority.
5083 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
5084 * 0 - Ignore incoming priority Pause frames on the specified priority
5086 * 1 - Respect incoming priority Pause frames on the specified priority.
5190 * Priority for counter set that support per priority, valid values: 0-7.
5628 * Configures the switch priority to buffer table.
5666 * Bit <i> is a flag for updating the mapping for switch priority <i>.
5672 * Mapping of switch priority <i> to one of the allocated receive port
5680 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5690 * Spectrum, as it maps untagged packets based on the default switch priority.
5695 * Mapping of switch priority <i+8> to one of the allocated receive port
6470 * Trap group priority.
6473 * register HPKT) with the highest priority.
6474 * Supported values are 0-7, with 7 represnting the highest priority.
6477 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
6480 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6503 u8 priority, u8 tc)
6520 mlxsw_reg_htgt_priority_set(payload, priority);
6651 * Update switch priority and packet color.
7440 * Controls the mapping from DSCP field to switch priority on routed packets
12609 * Association of the port-priority to a pool.
12757 * Association of the port-priority to a pool.
12818 * Bit vector for all switch priority groups.
12820 * are affected by the set operation. Configuration of any other priority