Lines Matching defs:enable
1695 * to enable VLAN stacking.
1813 * Virtual port enable.
1821 bool enable)
1825 mlxsw_reg_svpe_vp_en_set(payload, enable);
2095 * Vlan Tag1 EtherType2 enable.
2100 * 1: enable
2106 * Vlan Tag0 EtherType2 enable.
2110 * 1: enable
2116 * Vlan Tag1 EtherType1 enable.
2121 * 1: enable (default)
2127 * Vlan Tag0 EtherType1 enable.
2131 * 1: enable (default)
2137 * Vlan Tag1 EtherType0 enable.
2142 * 1: enable (default)
2148 * Vlan Tag0 EtherType0 enable.
2152 * 1: enable (default)
2162 /* Enable inner_et1 and inner_et0 to enable identification of double
3561 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
4058 * Min shaper configuration enable. Enables configuration of the min
4106 * Max shaper configuration enable. Enables configuration of the max
4126 * DWRR configuration enable. Enables configuration of the dwrr and
4191 * This register configures the rewrite enable per receive port.
4207 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
4213 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
4489 * Write enable to port_to_shaper_credits.
4943 * Event update enable. If this bit is set, event generation will be
5900 * be enabled upon explicit enable command.
5914 * Admin state update enable.
5922 * Event update enable.
5969 * Loopback enable.
6049 * The PMECR register is used to enable/disable event triggering
6064 * Event update enable. If this bit is set, event generation will be updated
6071 * Software ignore enable bit. If this bit is set, the value of swi is used.
6632 * IPv4 router enable.
6638 * IPv6 router enable.
6708 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6711 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
6718 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
6725 * IPv4 multicast routing enable.
6731 * IPv6 multicast routing enable.
6810 * Loop-back filter enable for unicast packets.
7031 bool enable, bool egress)
7035 if (enable)
7064 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
7068 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
7071 mlxsw_reg_ritr_enable_set(payload, enable);
7094 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id,
7100 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu);
8888 * Packet fields to enable for ECMP hash subject to outer_header_enable.
8930 * Inner packet fields to enable for ECMP hash subject to inner_header_enables.
9149 * Update enable (when write):
9764 * For an enabled analyzer, all fields except e (enable) cannot be modified.
9842 * Policer enable.
10017 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10038 bool enable, u8 pa_id,
10043 mlxsw_reg_mpar_enable_set(payload, enable);
10235 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10751 * Parsing enable.
10864 * This register is used to configure the mirror enable for different mirror
10896 * TClass/PG mirror enable. Each bit represents corresponding tclass.
10898 * 1: enable
11080 * non-sufficient condition since need to enable also per port. See MTPPPC.
11166 * 1 - check FW fatal - enable MFDE trap
11479 * Slot info event enable.
12293 * Trap enable:
12295 * 1 - Trap enable with trap_id
12447 * Trap enable:
12449 * 1 - Trap enable with trap_id