Lines Matching refs:entries
163 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
1715 * Reserved MTT entries must be aligned up to a cacheline
1717 * writes to all other MTT entries. (The variable
2963 struct msix_entry *entries;
2976 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
2977 if (!entries)
2981 entries[i].entry = i;
2983 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2987 kfree(entries);
2993 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
3002 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
3038 kfree(entries);