Lines Matching defs:param
1833 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1976 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1977 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1978 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1979 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1980 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1981 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1982 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1983 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1984 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1985 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1986 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1987 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1988 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1997 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1998 MLX4_PUT(inbox, param->log_mc_entry_sz,
2000 MLX4_PUT(inbox, param->log_mc_table_sz,
2027 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
2028 MLX4_PUT(inbox, param->log_mc_entry_sz,
2030 MLX4_PUT(inbox, param->log_mc_hash_sz,
2032 MLX4_PUT(inbox, param->log_mc_table_sz,
2041 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
2042 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
2043 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
2044 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
2045 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
2049 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2050 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
2069 struct mlx4_init_hca_param *param)
2100 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
2101 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2106 param->qpc_base = qword_field & ~((u64)0x1f);
2108 param->log_num_qps = byte_field & 0x1f;
2110 param->srqc_base = qword_field & ~((u64)0x1f);
2112 param->log_num_srqs = byte_field & 0x1f;
2114 param->cqc_base = qword_field & ~((u64)0x1f);
2116 param->log_num_cqs = byte_field & 0x1f;
2118 param->altc_base = qword_field;
2120 param->auxc_base = qword_field;
2122 param->eqc_base = qword_field & ~((u64)0x1f);
2124 param->log_num_eqs = byte_field & 0x1f;
2126 param->num_sys_eqs = word_field & 0xfff;
2128 param->rdmarc_base = qword_field & ~((u64)0x1f);
2130 param->log_rd_per_qp = byte_field & 0x7;
2134 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2138 param->steering_mode = MLX4_STEERING_MODE_B0;
2140 param->steering_mode = MLX4_STEERING_MODE_A0;
2144 param->rss_ip_frags = 1;
2147 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2148 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2150 param->log_mc_entry_sz = byte_field & 0x1f;
2152 param->log_mc_table_sz = byte_field & 0x1f;
2154 param->dmfs_high_steer_mode =
2157 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2159 param->log_mc_entry_sz = byte_field & 0x1f;
2161 param->log_mc_hash_sz = byte_field & 0x1f;
2163 param->log_mc_table_sz = byte_field & 0x1f;
2169 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
2171 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
2176 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
2177 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
2178 param->cqe_size = 1 << ((byte_field &
2180 param->eqe_size = 1 << (((byte_field &
2186 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
2188 param->mw_enabled = byte_field >> 7;
2190 param->log_mpt_sz = byte_field & 0x3f;
2191 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2192 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2196 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2198 param->log_uar_sz = byte_field & 0xf;
2203 param->phv_check_en = 1;