Lines Matching defs:mfunc
258 u32 status = readl(&priv->mfunc.comm->slave_read);
283 &priv->mfunc.comm->slave_write);
516 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
957 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
1666 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1683 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1684 priv->mfunc.master.slave_state[slave].vhcr_dma,
1820 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1821 priv->mfunc.master.slave_state[slave].vhcr_dma,
1829 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1851 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1852 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1861 if (!(priv->mfunc.master.slave_state[slave].active &&
1932 queue_work(priv->mfunc.master.comm_wq, &work->work);
1942 port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1965 port_qos = &priv->mfunc.master.qos_ctl[port];
2001 &priv->mfunc.master.slave_state[slave];
2007 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2008 priv->mfunc.master.vf_admin[slave].enable_smi[port];
2009 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2010 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2068 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2070 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2088 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2136 priv->mfunc.master.slave_state[slave].cookie = 0;
2178 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2183 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2190 &priv->mfunc.comm[slave].slave_read);
2208 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2211 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2217 &priv->mfunc.comm[slave].slave_read);
2228 struct mlx4_mfunc *mfunc =
2231 container_of(mfunc, struct mlx4_priv, mfunc);
2261 comm_cmd = swab32(readl(&mfunc->comm[slave].slave_write));
2262 slt = swab32(readl(&mfunc->comm[slave].slave_read)) >> 31;
2296 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2303 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2318 wr_toggle = swab32(readl(&priv->mfunc.comm->
2338 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2339 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2352 priv->mfunc.comm =
2357 priv->mfunc.comm =
2360 if (!priv->mfunc.comm) {
2369 priv->mfunc.master.slave_state =
2373 if (!priv->mfunc.master.slave_state)
2376 priv->mfunc.master.vf_admin =
2380 if (!priv->mfunc.master.vf_admin)
2383 priv->mfunc.master.vf_oper =
2387 if (!priv->mfunc.master.vf_oper)
2390 priv->mfunc.master.next_slave = 0;
2393 vf_admin = &priv->mfunc.master.vf_admin[i];
2394 vf_oper = &priv->mfunc.master.vf_oper[i];
2395 s_state = &priv->mfunc.master.slave_state[i];
2398 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2402 &priv->mfunc.comm[i].slave_write);
2404 &priv->mfunc.comm[i].slave_read);
2444 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
2445 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2446 INIT_WORK(&priv->mfunc.master.comm_work,
2448 INIT_WORK(&priv->mfunc.master.slave_event_work,
2450 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2452 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2453 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2454 priv->mfunc.master.comm_wq =
2456 if (!priv->mfunc.master.comm_wq)
2472 destroy_workqueue(priv->mfunc.master.comm_wq);
2476 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2478 kfree(priv->mfunc.master.vf_oper);
2480 kfree(priv->mfunc.master.vf_admin);
2482 kfree(priv->mfunc.master.slave_state);
2484 iounmap(priv->mfunc.comm);
2485 priv->mfunc.comm = NULL;
2488 priv->mfunc.vhcr,
2489 priv->mfunc.vhcr_dma);
2490 priv->mfunc.vhcr = NULL;
2519 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2520 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2522 &priv->mfunc.vhcr_dma,
2524 if (!priv->mfunc.vhcr)
2558 if (!priv->mfunc.comm)
2565 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2568 &priv->mfunc.comm[slave].slave_read);
2578 destroy_workqueue(priv->mfunc.master.comm_wq);
2581 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2583 kfree(priv->mfunc.master.slave_state);
2584 kfree(priv->mfunc.master.vf_admin);
2585 kfree(priv->mfunc.master.vf_oper);
2589 iounmap(priv->mfunc.comm);
2590 priv->mfunc.comm = NULL;
2607 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2610 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2611 priv->mfunc.vhcr = NULL;
2887 port_qos = &priv->mfunc.master.qos_ctl[port];
2934 info = &priv->mfunc.master.qos_ctl[port];
2992 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3039 slave_state = &priv->mfunc.master.slave_state[slave];
3046 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3047 vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3101 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3134 if (priv->mfunc.master.slave_state[slave].active &&
3154 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3183 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3210 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3272 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3380 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3396 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3425 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;