Lines Matching defs:ctrl
158 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
159 if (ctrl == 0xffff)
162 if (!(ctrl & GM_SMI_CT_BUSY))
184 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
185 if (ctrl == 0xffff)
188 if (ctrl & GM_SMI_CT_RD_VAL) {
327 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
348 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
365 ctrl &= ~PHY_M_PC_EN_DET_MSK;
368 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374 ctrl &= ~PHY_M_PC_DSC_MSK;
375 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 ctrl &= ~PHY_M_PC_MDIX_MSK;
385 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
394 ctrl &= ~PHY_M_MAC_MD_MSK;
395 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
396 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
404 ctrl |= PHY_M_FIB_SIGD_POL;
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 ctrl = PHY_CT_RESET;
439 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 ctrl |= PHY_CT_SP1000;
453 ctrl |= PHY_CT_SP100;
460 ctrl |= PHY_CT_DUP_MD;
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
718 u16 ctrl;
730 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
732 ctrl &= ~PHY_M_MAC_GMIF_PUP;
733 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
750 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
752 ctrl |= PHY_M_PC_POW_D_ENA;
753 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
811 u16 ctrl;
824 ctrl = sky2->advertising;
835 sky2->advertising = ctrl;
848 ctrl = 0;
850 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
852 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
855 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
857 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
859 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
860 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
1104 le->ctrl = 0;
1136 le->ctrl = 0;
1270 le->ctrl = 0;
1835 u8 ctrl;
1879 ctrl = 0;
1890 ctrl |= INS_VLAN;
1897 ctrl |= CALSUM; /* auto checksum */
1905 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1907 ctrl |= UDPTCP;
1915 le->ctrl = 1; /* one packet */
1929 le->ctrl = ctrl;
1958 le->ctrl = ctrl;
1963 le->ctrl |= EOP;
2067 u16 ctrl;
2079 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2080 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2081 gma_write16(hw, port, GM_GP_CTRL, ctrl);
4464 if (le->ctrl & EOP) {