Lines Matching refs:skge_write32
179 skge_write32(hw, B2_GP_IO, reg);
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
677 skge_write32(hw, B2_IRQM_MSK, msk);
679 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
681 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
682 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
700 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
704 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
726 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
1148 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1569 skge_write32(hw, B2_GP_IO, r);
1727 skge_write32(hw, B2_GP_IO, reg);
2060 skge_write32(hw, B2_FAR, reg);
2076 skge_write32(hw, B2_GP_IO, reg);
2080 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2081 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2089 skge_write32(hw, B2_GP_IO, reg);
2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2099 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2100 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2128 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2495 skge_write32(hw, RB_ADDR(q, RB_START), start);
2496 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2497 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2498 skge_write32(hw, RB_ADDR(q, RB_END), end);
2502 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2504 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2528 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2529 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2530 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2531 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2620 skge_write32(hw, B0_IMSK, hw->intr_mask);
2647 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2649 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2673 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2688 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2697 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2698 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2701 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2702 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
3237 skge_write32(hw, B0_IMSK, hw->intr_mask);
3309 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3315 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3371 skge_write32(hw, B0_IMSK, hw->intr_mask);
3436 skge_write32(hw, B0_IMSK, hw->intr_mask);
3666 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3671 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3672 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3673 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3676 skge_write32(hw, B0_IMSK, 0);
4044 skge_write32(hw, B0_IMSK, 0);
4084 skge_write32(hw, B0_IMSK, 0);