Lines Matching refs:port
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
163 int port = skge->port;
167 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
195 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
199 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
200 gm_phy_write(hw, port, PHY_MARV_CTRL,
206 gma_write16(hw, port, GM_GP_CTRL,
211 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
215 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
228 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
231 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
302 cmd->base.port = PORT_TP;
305 cmd->base.port = PORT_FIBRE;
627 int port = skge->port;
636 if (msk & rxirqmask[port])
638 if (msk & txirqmask[port])
645 /* Note: interrupt timer is per board, but can turn on/off per port */
653 int port = skge->port;
658 msk &= ~rxirqmask[port];
663 msk |= rxirqmask[port];
668 msk &= ~txirqmask[port];
673 msk |= txirqmask[port];
691 int port = skge->port;
698 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
700 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
701 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
704 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
709 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
710 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
718 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
720 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
725 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
726 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
727 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
734 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
735 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
743 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
756 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
1059 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1074 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1081 static void xm_link_down(struct skge_hw *hw, int port)
1083 struct net_device *dev = hw->dev[port];
1086 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1092 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1096 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1097 *val = xm_read16(hw, port, XM_PHY_DATA);
1103 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1110 *val = xm_read16(hw, port, XM_PHY_DATA);
1115 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1118 if (__xm_phy_read(hw, port, reg, &v))
1119 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1123 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1127 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1129 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1136 xm_write16(hw, port, XM_PHY_DATA, val);
1138 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1173 static void genesis_reset(struct skge_hw *hw, int port)
1178 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1181 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1182 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1183 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1184 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1185 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1189 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1191 xm_outhash(hw, port, XM_HSM, zero);
1194 reg = xm_read32(hw, port, XM_MODE);
1195 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1196 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1217 static void bcom_check_link(struct skge_hw *hw, int port)
1219 struct net_device *dev = hw->dev[port];
1224 xm_phy_read(hw, port, PHY_BCOM_STAT);
1225 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1228 xm_link_down(hw, port);
1238 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1244 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1286 int port = skge->port;
1305 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1308 r = xm_read16(hw, port, XM_MMU_CMD);
1310 xm_write16(hw, port, XM_MMU_CMD, r);
1319 xm_phy_write(hw, port,
1329 xm_phy_write(hw, port,
1338 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1340 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1343 xm_read16(hw, port, XM_ISRC);
1359 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1366 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1370 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1374 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1375 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1382 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1383 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1386 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1392 int port = skge->port;
1403 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1417 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1427 int port = skge->port;
1431 xm_phy_read(hw, port, PHY_XMAC_STAT);
1432 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1435 xm_link_down(hw, port);
1445 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1451 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1501 int port = skge->port;
1515 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1521 u16 msk = xm_read16(hw, port, XM_IMSK);
1523 xm_write16(hw, port, XM_IMSK, msk);
1524 xm_read16(hw, port, XM_ISRC);
1533 static void genesis_mac_init(struct skge_hw *hw, int port)
1535 struct net_device *dev = hw->dev[port];
1537 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1543 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1545 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1554 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1564 if (port == 0)
1572 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1582 bcom_check_link(hw, port);
1586 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1590 xm_outaddr(hw, port, XM_EXM(i), zero);
1593 xm_write16(hw, port, XM_STAT_CMD,
1596 xm_write16(hw, port, XM_STAT_CMD,
1600 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1615 xm_write16(hw, port, XM_RX_CMD, r);
1618 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1620 /* Increase threshold for jumbo frames on dual port */
1622 xm_write16(hw, port, XM_TX_THR, 1020);
1624 xm_write16(hw, port, XM_TX_THR, 512);
1640 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1648 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1655 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1672 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1673 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1674 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1677 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1678 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1679 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1683 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1687 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1694 int port = skge->port;
1699 cmd = xm_read16(hw, port, XM_MMU_CMD);
1701 xm_write16(hw, port, XM_MMU_CMD, cmd);
1703 genesis_reset(hw, port);
1707 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1710 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1712 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1713 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1720 if (port == 0) {
1731 xm_write16(hw, port, XM_MMU_CMD,
1732 xm_read16(hw, port, XM_MMU_CMD)
1735 xm_read16(hw, port, XM_MMU_CMD);
1742 int port = skge->port;
1746 xm_write16(hw, port,
1750 while (xm_read16(hw, port, XM_STAT_CMD)
1758 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1759 | xm_read32(hw, port, XM_TXO_OK_LO);
1760 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1761 | xm_read32(hw, port, XM_RXO_OK_LO);
1764 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1767 static void genesis_mac_intr(struct skge_hw *hw, int port)
1769 struct net_device *dev = hw->dev[port];
1771 u16 status = xm_read16(hw, port, XM_ISRC);
1777 xm_link_down(hw, port);
1782 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1790 int port = skge->port;
1794 cmd = xm_read16(hw, port, XM_MMU_CMD);
1808 xm_write16(hw, port, XM_MMU_CMD, cmd);
1810 mode = xm_read32(hw, port, XM_MODE);
1824 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1827 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1836 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1839 xm_write32(hw, port, XM_MODE, mode);
1842 msk = xm_read16(hw, port, XM_IMSK);
1844 xm_write16(hw, port, XM_IMSK, msk);
1846 xm_read16(hw, port, XM_ISRC);
1849 cmd = xm_read16(hw, port, XM_MMU_CMD);
1858 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1859 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1861 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1865 xm_write16(hw, port, XM_MMU_CMD,
1874 int port = skge->port;
1877 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1883 hw->dev[port]->name);
1889 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1890 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1892 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1897 bcom_check_link(hw, port);
1901 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1905 gma_write16(hw, port, GM_SMI_DATA, val);
1906 gma_write16(hw, port, GM_SMI_CTRL,
1911 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1915 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1919 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1923 gma_write16(hw, port, GM_SMI_CTRL,
1929 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1935 *val = gma_read16(hw, port, GM_SMI_DATA);
1939 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1942 if (__gm_phy_read(hw, port, reg, &v))
1943 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1948 static void yukon_init(struct skge_hw *hw, int port)
1950 struct skge_port *skge = netdev_priv(hw->dev[port]);
1954 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1962 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1965 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1970 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2023 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2025 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2026 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2032 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2035 static void yukon_reset(struct skge_hw *hw, int port)
2037 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2038 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2039 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2040 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2041 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2043 gma_write16(hw, port, GM_RX_CTRL,
2044 gma_read16(hw, port, GM_RX_CTRL)
2064 static void yukon_mac_init(struct skge_hw *hw, int port)
2066 struct skge_port *skge = netdev_priv(hw->dev[port]);
2069 const u8 *addr = hw->dev[port]->dev_addr;
2080 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2081 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2099 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2100 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2104 gma_write16(hw, port, GM_GP_CTRL,
2105 gma_read16(hw, port, GM_GP_CTRL) | reg);
2128 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2141 gma_write16(hw, port, GM_GP_CTRL, reg);
2142 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2144 yukon_init(hw, port);
2147 reg = gma_read16(hw, port, GM_PHY_ADDR);
2148 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2151 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2152 gma_write16(hw, port, GM_PHY_ADDR, reg);
2155 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2158 gma_write16(hw, port, GM_RX_CTRL,
2162 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2165 gma_write16(hw, port, GM_TX_PARAM,
2175 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2178 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2181 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2183 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2186 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2187 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2188 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2193 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2200 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2201 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2207 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2210 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2211 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2215 static void yukon_suspend(struct skge_hw *hw, int port)
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2221 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2223 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2225 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2230 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2236 int port = skge->port;
2238 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2239 yukon_reset(hw, port);
2241 gma_write16(hw, port, GM_GP_CTRL,
2242 gma_read16(hw, port, GM_GP_CTRL)
2244 gma_read16(hw, port, GM_GP_CTRL);
2246 yukon_suspend(hw, port);
2249 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2250 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2256 int port = skge->port;
2259 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2260 | gma_read32(hw, port, GM_TXO_OK_LO);
2261 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2262 | gma_read32(hw, port, GM_RXO_OK_LO);
2265 data[i] = gma_read32(hw, port,
2269 static void yukon_mac_intr(struct skge_hw *hw, int port)
2271 struct net_device *dev = hw->dev[port];
2273 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2285 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2305 int port = skge->port;
2309 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2311 reg = gma_read16(hw, port, GM_GP_CTRL);
2317 gma_write16(hw, port, GM_GP_CTRL, reg);
2319 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2326 int port = skge->port;
2329 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2331 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2334 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2337 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2342 yukon_init(hw, port);
2348 int port = skge->port;
2352 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2353 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2359 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2365 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2396 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2398 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2424 int port = skge->port;
2425 struct net_device *dev = hw->dev[port];
2432 genesis_reset(hw, port);
2433 genesis_mac_init(hw, port);
2435 yukon_reset(hw, port);
2436 yukon_init(hw, port);
2464 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2466 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2475 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2478 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2538 int port = skge->port;
2597 genesis_mac_init(hw, port);
2599 yukon_mac_init(hw, port);
2604 ram_addr = hw->ram_offset + 2 * chunk * port;
2606 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2607 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2610 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2611 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2615 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2619 hw->intr_mask |= portmask[port];
2644 static void skge_rx_stop(struct skge_hw *hw, int port)
2646 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2647 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2649 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2656 int port = skge->port;
2672 hw->intr_mask &= ~portmask[port];
2680 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2687 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2688 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2693 skge_write8(hw, SK_REG(port, TXA_CTRL),
2697 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2698 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2701 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2702 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2705 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2707 skge_rx_stop(hw, port);
2710 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2711 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2713 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2714 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2825 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2898 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2938 int port = skge->port;
2943 mode = xm_read32(hw, port, XM_MODE);
2963 xm_write32(hw, port, XM_MODE, mode);
2964 xm_outhash(hw, port, XM_HSM, filter);
2978 int port = skge->port;
2987 reg = gma_read16(hw, port, GM_RX_CTRL);
3007 gma_write16(hw, port, GM_MC_ADDR_H1,
3009 gma_write16(hw, port, GM_MC_ADDR_H2,
3011 gma_write16(hw, port, GM_MC_ADDR_H3,
3013 gma_write16(hw, port, GM_MC_ADDR_H4,
3016 gma_write16(hw, port, GM_RX_CTRL, reg);
3158 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3208 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3230 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3236 hw->intr_mask |= napimask[skge->port];
3248 static void skge_mac_parity(struct skge_hw *hw, int port)
3250 struct net_device *dev = hw->dev[port];
3255 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3259 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3264 static void skge_mac_intr(struct skge_hw *hw, int port)
3267 genesis_mac_intr(hw, port);
3269 yukon_mac_intr(hw, port);
3352 int port;
3354 for (port = 0; port < hw->ports; port++) {
3355 struct net_device *dev = hw->dev[port];
3458 unsigned port = skge->port;
3468 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3469 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3473 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3474 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3476 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3477 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3480 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3483 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3486 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3519 * the port(s)
3675 /* Leave irq disabled until first port is brought up. */
3811 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3855 hw->dev[port] = dev;
3857 skge->port = port;
3869 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);