Lines Matching refs:SMI
46 #define SMI 0x0010
1290 /* wait for the SMI register to become available */
1291 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1307 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1310 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1312 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1315 "pxa168_eth: SMI bus read not valid\n");
1330 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1334 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1338 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n");