Lines Matching defs:offset
361 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
394 unsigned short offset;
762 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
764 writel(data, pp->base + offset);
768 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
770 return readl(pp->base + offset);
944 /* Set rx queue offset */
947 int offset)
955 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
1377 int offset;
1387 for (offset = 0; offset <= 0xc; offset += 4)
1388 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1394 int offset;
1404 for (offset = 0; offset <= 0xfc; offset += 4)
1405 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1412 int offset;
1424 for (offset = 0; offset <= 0xfc; offset += 4)
1425 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1643 /* offset from unicast tbl base */
1646 /* offset within the above reg */
2708 int index, offset;
2711 offset = (txq->txq_put_index % MVNETA_TSO_PER_PAGE) * TSO_HEADER_SIZE;
2713 *dma = txq->tso_hdrs_phys[index] + offset;
2715 return txq->tso_hdrs[index] + offset;
3079 /* Register offset from SMC table base */
3081 /* Entry offset within the above reg */
3114 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
3115 reg_offset = crc8 % 4; /* Entry offset within the above reg */
3357 .offset = pp->rx_offset_correction,
4867 val = readl_relaxed(base + s->offset);
4872 low = readl_relaxed(base + s->offset);
4873 high = readl_relaxed(base + s->offset + 4);
4878 switch (s->offset) {
5244 mqprio->qopt.offset[tc]);
5246 for (rxq = mqprio->qopt.offset[tc];
5247 rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
5269 for (txq = mqprio->qopt.offset[tc];
5270 txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
5648 /* Set RX packet offset correction for platforms, whose