Lines Matching defs:mvreg_read
768 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
797 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
798 mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
799 mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
880 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
936 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
951 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1008 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
1022 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1033 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1044 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1057 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1078 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1090 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1117 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1284 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1302 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1308 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1326 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1341 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1354 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1365 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1576 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1604 val = mvreg_read(pp, MVNETA_TX_MTU);
1610 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1620 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1649 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1713 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1758 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
3084 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
3117 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
3178 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
3180 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
3260 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3286 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3288 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3927 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3928 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3984 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
4051 old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4064 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4102 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4127 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
4128 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
4129 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
4172 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4187 clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
4200 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4212 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
4230 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4251 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4276 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4361 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
5104 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
5126 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
5146 u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
5171 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
5183 u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);