Lines Matching defs:jme
33 #include "jme.h"
50 struct jme_adapter *jme = netdev_priv(netdev);
54 jwrite32(jme, JME_SMI, SMI_OP_REQ |
61 val = jread32(jme, JME_SMI);
81 struct jme_adapter *jme = netdev_priv(netdev);
84 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
91 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 jme_reset_phy_processor(struct jme_adapter *jme)
104 jme_mdio_write(jme->dev,
105 jme->mii_if.phy_id,
109 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
110 jme_mdio_write(jme->dev,
111 jme->mii_if.phy_id,
115 val = jme_mdio_read(jme->dev,
116 jme->mii_if.phy_id,
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
125 jme_setup_wakeup_frame(struct jme_adapter *jme,
133 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
135 jwrite32(jme, JME_WFODP, crc);
142 jwrite32(jme, JME_WFOI,
146 jwrite32(jme, JME_WFODP, mask[i]);
152 jme_mac_rxclk_off(struct jme_adapter *jme)
154 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
155 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
159 jme_mac_rxclk_on(struct jme_adapter *jme)
161 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
162 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
166 jme_mac_txclk_off(struct jme_adapter *jme)
168 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
169 jwrite32f(jme, JME_GHC, jme->reg_ghc);
173 jme_mac_txclk_on(struct jme_adapter *jme)
175 u32 speed = jme->reg_ghc & GHC_SPEED;
177 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
179 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
180 jwrite32f(jme, JME_GHC, jme->reg_ghc);
184 jme_reset_ghc_speed(struct jme_adapter *jme)
186 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
187 jwrite32f(jme, JME_GHC, jme->reg_ghc);
191 jme_reset_250A2_workaround(struct jme_adapter *jme)
193 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
195 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
199 jme_assert_ghc_reset(struct jme_adapter *jme)
201 jme->reg_ghc |= GHC_SWRST;
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
206 jme_clear_ghc_reset(struct jme_adapter *jme)
208 jme->reg_ghc &= ~GHC_SWRST;
209 jwrite32f(jme, JME_GHC, jme->reg_ghc);
213 jme_reset_mac_processor(struct jme_adapter *jme)
220 jme_reset_ghc_speed(jme);
221 jme_reset_250A2_workaround(jme);
223 jme_mac_rxclk_on(jme);
224 jme_mac_txclk_on(jme);
226 jme_assert_ghc_reset(jme);
228 jme_mac_rxclk_off(jme);
229 jme_mac_txclk_off(jme);
231 jme_clear_ghc_reset(jme);
233 jme_mac_rxclk_on(jme);
234 jme_mac_txclk_on(jme);
236 jme_mac_rxclk_off(jme);
237 jme_mac_txclk_off(jme);
239 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
240 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
241 jwrite32(jme, JME_RXQDC, 0x00000000);
242 jwrite32(jme, JME_RXNDA, 0x00000000);
243 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
244 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
245 jwrite32(jme, JME_TXQDC, 0x00000000);
246 jwrite32(jme, JME_TXNDA, 0x00000000);
248 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
249 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
251 jme_setup_wakeup_frame(jme, mask, crc, i);
252 if (jme->fpgaver)
256 jwrite32(jme, JME_GPREG0, gpreg0);
260 jme_clear_pm_enable_wol(struct jme_adapter *jme)
262 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
266 jme_clear_pm_disable_wol(struct jme_adapter *jme)
268 jwrite32(jme, JME_PMCS, PMCS_STMASK);
272 jme_reload_eeprom(struct jme_adapter *jme)
277 val = jread32(jme, JME_SMBCSR);
281 jwrite32(jme, JME_SMBCSR, val);
283 jwrite32(jme, JME_SMBCSR, val);
288 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
304 struct jme_adapter *jme = netdev_priv(netdev);
308 spin_lock_bh(&jme->macaddr_lock);
309 val = jread32(jme, JME_RXUMA_LO);
314 val = jread32(jme, JME_RXUMA_HI);
318 spin_unlock_bh(&jme->macaddr_lock);
322 jme_set_rx_pcc(struct jme_adapter *jme, int p)
326 jwrite32(jme, JME_PCCRX0,
331 jwrite32(jme, JME_PCCRX0,
336 jwrite32(jme, JME_PCCRX0,
341 jwrite32(jme, JME_PCCRX0,
350 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
351 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
355 jme_start_irq(struct jme_adapter *jme)
357 register struct dynpcc_info *dpi = &(jme->dpi);
359 jme_set_rx_pcc(jme, PCC_P1);
364 jwrite32(jme, JME_PCCTX,
373 jwrite32(jme, JME_IENS, INTR_ENABLE);
377 jme_stop_irq(struct jme_adapter *jme)
382 jwrite32f(jme, JME_IENC, INTR_ENABLE);
386 jme_linkstat_from_phy(struct jme_adapter *jme)
390 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
391 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
399 jme_set_phyfifo_5level(struct jme_adapter *jme)
401 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
405 jme_set_phyfifo_8level(struct jme_adapter *jme)
407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
413 struct jme_adapter *jme = netdev_priv(netdev);
420 if (jme->fpgaver)
421 phylink = jme_linkstat_from_phy(jme);
423 phylink = jread32(jme, JME_PHY_LINK);
433 bmcr = jme_mdio_read(jme->dev,
434 jme->mii_if.phy_id,
457 if (jme->fpgaver)
458 phylink = jme_linkstat_from_phy(jme);
460 phylink = jread32(jme, JME_PHY_LINK);
468 if (jme->phylink == phylink) {
475 jme->phylink = phylink;
478 * The speed/duplex setting of jme->reg_ghc already cleared
483 jme->reg_ghc |= GHC_SPEED_10M;
487 jme->reg_ghc |= GHC_SPEED_100M;
491 jme->reg_ghc |= GHC_SPEED_1000M;
499 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
500 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
501 jme->reg_ghc |= GHC_DPX;
503 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
507 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
510 jwrite32(jme, JME_GHC, jme->reg_ghc);
512 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
513 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
516 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
519 jme_set_phyfifo_8level(jme);
520 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
523 jme_set_phyfifo_5level(jme);
524 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
527 jme_set_phyfifo_8level(jme);
533 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
541 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
547 netif_info(jme, link, jme->dev, "Link is down\n");
548 jme->phylink = 0;
557 jme_setup_tx_resources(struct jme_adapter *jme)
559 struct jme_ring *txring = &(jme->txring[0]);
561 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
562 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577 atomic_set(&txring->nr_free, jme->tx_ring_size);
579 txring->bufinf = kcalloc(jme->tx_ring_size,
588 dma_free_coherent(&(jme->pdev->dev),
589 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
603 jme_free_tx_resources(struct jme_adapter *jme)
606 struct jme_ring *txring = &(jme->txring[0]);
611 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
625 dma_free_coherent(&(jme->pdev->dev),
626 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
642 jme_enable_tx_engine(struct jme_adapter *jme)
647 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
653 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
654 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
655 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
660 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
666 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
673 jme_mac_txclk_on(jme);
677 jme_disable_tx_engine(struct jme_adapter *jme)
685 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
688 val = jread32(jme, JME_TXCS);
691 val = jread32(jme, JME_TXCS);
701 jme_mac_txclk_off(jme);
705 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
707 struct jme_ring *rxring = &(jme->rxring[0]);
719 if (jme->dev->features & NETIF_F_HIGHDMA)
726 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
728 struct jme_ring *rxring = &(jme->rxring[0]);
733 skb = netdev_alloc_skb(jme->dev,
734 jme->dev->mtu + RX_EXTRA_LEN);
738 mapping = dma_map_page(&jme->pdev->dev, virt_to_page(skb->data),
741 if (unlikely(dma_mapping_error(&jme->pdev->dev, mapping))) {
747 dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
757 jme_free_rx_buf(struct jme_adapter *jme, int i)
759 struct jme_ring *rxring = &(jme->rxring[0]);
764 dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
774 jme_free_rx_resources(struct jme_adapter *jme)
777 struct jme_ring *rxring = &(jme->rxring[0]);
781 for (i = 0 ; i < jme->rx_ring_size ; ++i)
782 jme_free_rx_buf(jme, i);
786 dma_free_coherent(&(jme->pdev->dev),
787 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
801 jme_setup_rx_resources(struct jme_adapter *jme)
804 struct jme_ring *rxring = &(jme->rxring[0]);
806 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
807 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
822 rxring->bufinf = kcalloc(jme->rx_ring_size,
831 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
832 if (unlikely(jme_make_new_rx_buf(jme, i))) {
833 jme_free_rx_resources(jme);
837 jme_set_clean_rxdesc(jme, i);
843 dma_free_coherent(&(jme->pdev->dev),
844 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
857 jme_enable_rx_engine(struct jme_adapter *jme)
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
869 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
870 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
871 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
876 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
881 jme_set_unicastaddr(jme->dev);
882 jme_set_multi(jme->dev);
888 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
896 jme_mac_rxclk_on(jme);
900 jme_restart_rx_engine(struct jme_adapter *jme)
905 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
912 jme_disable_rx_engine(struct jme_adapter *jme)
920 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
923 val = jread32(jme, JME_RXCS);
926 val = jread32(jme, JME_RXCS);
936 jme_mac_rxclk_off(jme);
966 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
974 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
981 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
987 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
995 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
997 struct jme_ring *rxring = &(jme->rxring[0]);
1007 dma_sync_single_for_cpu(&jme->pdev->dev, rxbi->mapping, rxbi->len,
1010 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1011 dma_sync_single_for_device(&jme->pdev->dev, rxbi->mapping,
1014 ++(NET_STAT(jme).rx_dropped);
1021 skb->protocol = eth_type_trans(skb, jme->dev);
1023 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1032 NET_STAT(jme).rx_bytes += 4;
1034 jme->jme_rx(skb);
1038 ++(NET_STAT(jme).multicast);
1040 NET_STAT(jme).rx_bytes += framesize;
1041 ++(NET_STAT(jme).rx_packets);
1044 jme_set_clean_rxdesc(jme, idx);
1049 jme_process_receive(struct jme_adapter *jme, int limit)
1051 struct jme_ring *rxring = &(jme->rxring[0]);
1053 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1055 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1058 if (unlikely(atomic_read(&jme->link_changing) != 1))
1061 if (unlikely(!netif_carrier_ok(jme->dev)))
1081 ++(NET_STAT(jme).rx_crc_errors);
1083 ++(NET_STAT(jme).rx_fifo_errors);
1085 ++(NET_STAT(jme).rx_errors);
1091 jme_set_clean_rxdesc(jme, j);
1096 jme_alloc_and_feed_skb(jme, i);
1106 atomic_inc(&jme->rx_cleaning);
1130 jme_dynamic_pcc(struct jme_adapter *jme)
1132 register struct dynpcc_info *dpi = &(jme->dpi);
1134 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1136 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1144 tasklet_schedule(&jme->rxclean_task);
1145 jme_set_rx_pcc(jme, dpi->attempt);
1152 jme_start_pcc_timer(struct jme_adapter *jme)
1154 struct dynpcc_info *dpi = &(jme->dpi);
1155 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1156 dpi->last_pkts = NET_STAT(jme).rx_packets;
1158 jwrite32(jme, JME_TMCSR,
1163 jme_stop_pcc_timer(struct jme_adapter *jme)
1165 jwrite32(jme, JME_TMCSR, 0);
1169 jme_shutdown_nic(struct jme_adapter *jme)
1173 phylink = jme_linkstat_from_phy(jme);
1179 jme_stop_irq(jme);
1180 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1187 struct jme_adapter *jme = from_tasklet(jme, t, pcc_task);
1188 struct net_device *netdev = jme->dev;
1190 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1191 jme_shutdown_nic(jme);
1196 (atomic_read(&jme->link_changing) != 1)
1198 jme_stop_pcc_timer(jme);
1202 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1203 jme_dynamic_pcc(jme);
1205 jme_start_pcc_timer(jme);
1209 jme_polling_mode(struct jme_adapter *jme)
1211 jme_set_rx_pcc(jme, PCC_OFF);
1215 jme_interrupt_mode(struct jme_adapter *jme)
1217 jme_set_rx_pcc(jme, PCC_P1);
1221 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1224 apmc = jread32(jme, JME_APMC);
1229 jme_start_shutdown_timer(struct jme_adapter *jme)
1233 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1236 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1239 jwrite32f(jme, JME_APMC, apmc);
1241 jwrite32f(jme, JME_TIMER2, 0);
1242 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1243 jwrite32(jme, JME_TMCSR,
1248 jme_stop_shutdown_timer(struct jme_adapter *jme)
1252 jwrite32f(jme, JME_TMCSR, 0);
1253 jwrite32f(jme, JME_TIMER2, 0);
1254 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1256 apmc = jread32(jme, JME_APMC);
1258 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1260 jwrite32f(jme, JME_APMC, apmc);
1265 struct jme_adapter *jme = container_of(work, struct jme_adapter, linkch_task);
1266 struct net_device *netdev = jme->dev;
1269 while (!atomic_dec_and_test(&jme->link_changing)) {
1270 atomic_inc(&jme->link_changing);
1271 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1272 while (atomic_read(&jme->link_changing) != 1)
1273 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1276 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1279 jme->old_mtu = netdev->mtu;
1281 if (jme_pseudo_hotplug_enabled(jme))
1282 jme_stop_shutdown_timer(jme);
1284 jme_stop_pcc_timer(jme);
1285 tasklet_disable(&jme->txclean_task);
1286 tasklet_disable(&jme->rxclean_task);
1287 tasklet_disable(&jme->rxempty_task);
1290 jme_disable_rx_engine(jme);
1291 jme_disable_tx_engine(jme);
1292 jme_reset_mac_processor(jme);
1293 jme_free_rx_resources(jme);
1294 jme_free_tx_resources(jme);
1296 if (test_bit(JME_FLAG_POLL, &jme->flags))
1297 jme_polling_mode(jme);
1304 rc = jme_setup_rx_resources(jme);
1310 rc = jme_setup_tx_resources(jme);
1316 jme_enable_rx_engine(jme);
1317 jme_enable_tx_engine(jme);
1321 if (test_bit(JME_FLAG_POLL, &jme->flags))
1322 jme_interrupt_mode(jme);
1324 jme_start_pcc_timer(jme);
1325 } else if (jme_pseudo_hotplug_enabled(jme)) {
1326 jme_start_shutdown_timer(jme);
1332 jme_free_rx_resources(jme);
1334 tasklet_enable(&jme->txclean_task);
1335 tasklet_enable(&jme->rxclean_task);
1336 tasklet_enable(&jme->rxempty_task);
1338 atomic_inc(&jme->link_changing);
1344 struct jme_adapter *jme = from_tasklet(jme, t, rxclean_task);
1345 struct dynpcc_info *dpi = &(jme->dpi);
1347 jme_process_receive(jme, jme->rx_ring_size);
1355 struct jme_adapter *jme = jme_napi_priv(holder);
1358 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1360 while (atomic_read(&jme->rx_empty) > 0) {
1361 atomic_dec(&jme->rx_empty);
1362 ++(NET_STAT(jme).rx_dropped);
1363 jme_restart_rx_engine(jme);
1365 atomic_inc(&jme->rx_empty);
1369 jme_interrupt_mode(jme);
1379 struct jme_adapter *jme = from_tasklet(jme, t, rxempty_task);
1381 if (unlikely(atomic_read(&jme->link_changing) != 1))
1384 if (unlikely(!netif_carrier_ok(jme->dev)))
1387 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1389 jme_rx_clean_tasklet(&jme->rxclean_task);
1391 while (atomic_read(&jme->rx_empty) > 0) {
1392 atomic_dec(&jme->rx_empty);
1393 ++(NET_STAT(jme).rx_dropped);
1394 jme_restart_rx_engine(jme);
1396 atomic_inc(&jme->rx_empty);
1400 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1402 struct jme_ring *txring = &(jme->txring[0]);
1405 if (unlikely(netif_queue_stopped(jme->dev) &&
1406 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1407 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1408 netif_wake_queue(jme->dev);
1415 struct jme_adapter *jme = from_tasklet(jme, t, txclean_task);
1416 struct jme_ring *txring = &(jme->txring[0]);
1421 tx_dbg(jme, "Into txclean\n");
1423 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1426 if (unlikely(atomic_read(&jme->link_changing) != 1))
1429 if (unlikely(!netif_carrier_ok(jme->dev)))
1432 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1433 mask = jme->tx_ring_mask;
1442 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1451 dma_unmap_page(&jme->pdev->dev,
1464 ++(NET_STAT(jme).tx_carrier_errors);
1466 ++(NET_STAT(jme).tx_packets);
1467 NET_STAT(jme).tx_bytes += ctxbi->len;
1483 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1487 jme_wake_queue_if_stopped(jme);
1490 atomic_inc(&jme->tx_cleaning);
1494 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1499 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1506 jwrite32(jme, JME_IEVE, intrstat);
1507 schedule_work(&jme->linkch_task);
1512 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1513 tasklet_schedule(&jme->pcc_task);
1517 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1518 tasklet_schedule(&jme->txclean_task);
1522 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1528 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1530 atomic_inc(&jme->rx_empty);
1533 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1534 jme_polling_mode(jme);
1535 JME_RX_SCHEDULE(jme);
1540 atomic_inc(&jme->rx_empty);
1541 tasklet_hi_schedule(&jme->rxempty_task);
1543 tasklet_hi_schedule(&jme->rxclean_task);
1551 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1558 struct jme_adapter *jme = netdev_priv(netdev);
1561 intrstat = jread32(jme, JME_IEVE);
1575 jme_intr_msi(jme, intrstat);
1584 struct jme_adapter *jme = netdev_priv(netdev);
1587 intrstat = jread32(jme, JME_IEVE);
1589 jme_intr_msi(jme, intrstat);
1595 jme_reset_link(struct jme_adapter *jme)
1597 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1601 jme_restart_an(struct jme_adapter *jme)
1605 spin_lock_bh(&jme->phy_lock);
1606 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1608 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1609 spin_unlock_bh(&jme->phy_lock);
1613 jme_request_irq(struct jme_adapter *jme)
1616 struct net_device *netdev = jme->dev;
1620 if (!pci_enable_msi(jme->pdev)) {
1621 set_bit(JME_FLAG_MSI, &jme->flags);
1626 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1631 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1634 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1635 pci_disable_msi(jme->pdev);
1636 clear_bit(JME_FLAG_MSI, &jme->flags);
1639 netdev->irq = jme->pdev->irq;
1646 jme_free_irq(struct jme_adapter *jme)
1648 free_irq(jme->pdev->irq, jme->dev);
1649 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1650 pci_disable_msi(jme->pdev);
1651 clear_bit(JME_FLAG_MSI, &jme->flags);
1652 jme->dev->irq = jme->pdev->irq;
1657 jme_new_phy_on(struct jme_adapter *jme)
1661 reg = jread32(jme, JME_PHY_PWR);
1664 jwrite32(jme, JME_PHY_PWR, reg);
1666 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1669 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1673 jme_new_phy_off(struct jme_adapter *jme)
1677 reg = jread32(jme, JME_PHY_PWR);
1680 jwrite32(jme, JME_PHY_PWR, reg);
1682 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1685 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1689 jme_phy_on(struct jme_adapter *jme)
1693 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1695 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1697 if (new_phy_power_ctrl(jme->chip_main_rev))
1698 jme_new_phy_on(jme);
1702 jme_phy_off(struct jme_adapter *jme)
1706 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1708 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1710 if (new_phy_power_ctrl(jme->chip_main_rev))
1711 jme_new_phy_off(jme);
1715 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1720 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1722 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1727 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1732 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1734 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1739 jme_phy_calibration(struct jme_adapter *jme)
1743 jme_phy_off(jme);
1744 jme_phy_on(jme);
1746 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1749 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1751 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1755 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1757 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1761 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1764 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1766 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1771 jme_phy_setEA(struct jme_adapter *jme)
1776 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1780 switch (jme->pdev->device) {
1782 if (((jme->chip_main_rev == 5) &&
1783 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1784 (jme->chip_sub_rev == 3))) ||
1785 (jme->chip_main_rev >= 6)) {
1789 if ((jme->chip_main_rev == 3) &&
1790 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1794 if (((jme->chip_main_rev == 5) &&
1795 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1796 (jme->chip_sub_rev == 3))) ||
1797 (jme->chip_main_rev >= 6)) {
1801 if ((jme->chip_main_rev == 3) &&
1802 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1804 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1806 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1813 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1815 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1823 struct jme_adapter *jme = netdev_priv(netdev);
1826 jme_clear_pm_disable_wol(jme);
1827 JME_NAPI_ENABLE(jme);
1829 tasklet_setup(&jme->txclean_task, jme_tx_clean_tasklet);
1830 tasklet_setup(&jme->rxclean_task, jme_rx_clean_tasklet);
1831 tasklet_setup(&jme->rxempty_task, jme_rx_empty_tasklet);
1833 rc = jme_request_irq(jme);
1837 jme_start_irq(jme);
1839 jme_phy_on(jme);
1840 if (test_bit(JME_FLAG_SSET, &jme->flags))
1841 jme_set_link_ksettings(netdev, &jme->old_cmd);
1843 jme_reset_phy_processor(jme);
1844 jme_phy_calibration(jme);
1845 jme_phy_setEA(jme);
1846 jme_reset_link(jme);
1857 jme_set_100m_half(struct jme_adapter *jme)
1861 jme_phy_on(jme);
1862 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1868 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1870 if (jme->fpgaver)
1871 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1873 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1878 jme_wait_link(struct jme_adapter *jme)
1883 phylink = jme_linkstat_from_phy(jme);
1886 phylink = jme_linkstat_from_phy(jme);
1891 jme_powersave_phy(struct jme_adapter *jme)
1893 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1894 jme_set_100m_half(jme);
1895 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1896 jme_wait_link(jme);
1897 jme_clear_pm_enable_wol(jme);
1899 jme_phy_off(jme);
1906 struct jme_adapter *jme = netdev_priv(netdev);
1911 jme_stop_irq(jme);
1912 jme_free_irq(jme);
1914 JME_NAPI_DISABLE(jme);
1916 cancel_work_sync(&jme->linkch_task);
1917 tasklet_kill(&jme->txclean_task);
1918 tasklet_kill(&jme->rxclean_task);
1919 tasklet_kill(&jme->rxempty_task);
1921 jme_disable_rx_engine(jme);
1922 jme_disable_tx_engine(jme);
1923 jme_reset_mac_processor(jme);
1924 jme_free_rx_resources(jme);
1925 jme_free_tx_resources(jme);
1926 jme->phylink = 0;
1927 jme_phy_off(jme);
1933 jme_alloc_txdesc(struct jme_adapter *jme,
1936 struct jme_ring *txring = &(jme->txring[0]);
1937 int idx, nr_alloc, mask = jme->tx_ring_mask;
1985 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
1987 struct jme_ring *txring = &(jme->txring[0]);
1989 int mask = jme->tx_ring_mask;
1994 dma_unmap_page(&jme->pdev->dev, ctxbi->mapping, ctxbi->len,
2003 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2005 struct jme_ring *txring = &(jme->txring[0]);
2008 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
2010 int mask = jme->tx_ring_mask;
2020 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2024 jme_drop_tx_map(jme, idx, i);
2032 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2035 jme_drop_tx_map(jme, idx, i);
2069 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2094 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2110 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2112 struct jme_ring *txring = &(jme->txring[0]);
2139 jme_tx_csum(jme, skb, &flags);
2141 ret = jme_map_tx_skb(jme, skb, idx);
2162 jme_stop_queue_if_full(struct jme_adapter *jme)
2164 struct jme_ring *txring = &(jme->txring[0]);
2172 netif_stop_queue(jme->dev);
2173 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2176 >= (jme->tx_wake_threshold)) {
2177 netif_wake_queue(jme->dev);
2178 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2185 netif_stop_queue(jme->dev);
2186 netif_info(jme, tx_queued, jme->dev,
2198 struct jme_adapter *jme = netdev_priv(netdev);
2203 ++(NET_STAT(jme).tx_dropped);
2207 idx = jme_alloc_txdesc(jme, skb);
2211 netif_err(jme, tx_err, jme->dev,
2217 if (jme_fill_tx_desc(jme, skb, idx))
2220 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2225 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2227 jme_stop_queue_if_full(jme);
2235 struct jme_adapter *jme = netdev_priv(netdev);
2242 jwrite32(jme, JME_RXUMA_LO, val);
2245 jwrite32(jme, JME_RXUMA_HI, val);
2251 struct jme_adapter *jme = netdev_priv(netdev);
2257 spin_lock_bh(&jme->macaddr_lock);
2260 spin_unlock_bh(&jme->macaddr_lock);
2268 struct jme_adapter *jme = netdev_priv(netdev);
2271 spin_lock_bh(&jme->rxmcs_lock);
2273 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2276 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2278 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2283 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2289 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2290 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2294 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2296 spin_unlock_bh(&jme->rxmcs_lock);
2302 struct jme_adapter *jme = netdev_priv(netdev);
2307 jme_restart_rx_engine(jme);
2308 jme_reset_link(jme);
2316 struct jme_adapter *jme = netdev_priv(netdev);
2318 jme->phylink = 0;
2319 jme_reset_phy_processor(jme);
2320 if (test_bit(JME_FLAG_SSET, &jme->flags))
2321 jme_set_link_ksettings(netdev, &jme->old_cmd);
2326 jme_reset_link(jme);
2333 struct jme_adapter *jme = netdev_priv(netdev);
2337 strscpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
2347 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2352 p[i >> 2] = jread32(jme, reg + i);
2356 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2362 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2368 struct jme_adapter *jme = netdev_priv(netdev);
2374 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2377 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2380 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2383 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2386 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2394 struct jme_adapter *jme = netdev_priv(netdev);
2399 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2408 switch (jme->dpi.cur) {
2433 struct jme_adapter *jme = netdev_priv(netdev);
2434 struct dynpcc_info *dpi = &(jme->dpi);
2440 test_bit(JME_FLAG_POLL, &jme->flags)) {
2441 clear_bit(JME_FLAG_POLL, &jme->flags);
2442 jme->jme_rx = netif_rx;
2446 jme_set_rx_pcc(jme, PCC_P1);
2447 jme_interrupt_mode(jme);
2449 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2450 set_bit(JME_FLAG_POLL, &jme->flags);
2451 jme->jme_rx = netif_receive_skb;
2452 jme_interrupt_mode(jme);
2462 struct jme_adapter *jme = netdev_priv(netdev);
2465 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2466 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2468 spin_lock_bh(&jme->phy_lock);
2469 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2470 spin_unlock_bh(&jme->phy_lock);
2480 struct jme_adapter *jme = netdev_priv(netdev);
2483 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2487 jme->reg_txpfc |= TXPFC_PF_EN;
2489 jme->reg_txpfc &= ~TXPFC_PF_EN;
2491 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2494 spin_lock_bh(&jme->rxmcs_lock);
2495 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2499 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2501 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2503 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2505 spin_unlock_bh(&jme->rxmcs_lock);
2507 spin_lock_bh(&jme->phy_lock);
2508 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2517 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2520 spin_unlock_bh(&jme->phy_lock);
2529 struct jme_adapter *jme = netdev_priv(netdev);
2535 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2538 if (jme->reg_pmcs & PMCS_MFEN)
2547 struct jme_adapter *jme = netdev_priv(netdev);
2556 jme->reg_pmcs = 0;
2559 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2562 jme->reg_pmcs |= PMCS_MFEN;
2571 struct jme_adapter *jme = netdev_priv(netdev);
2573 spin_lock_bh(&jme->phy_lock);
2574 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
2575 spin_unlock_bh(&jme->phy_lock);
2583 struct jme_adapter *jme = netdev_priv(netdev);
2594 if (jme->mii_if.force_media &&
2596 (jme->mii_if.full_duplex != cmd->base.duplex))
2599 spin_lock_bh(&jme->phy_lock);
2600 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
2601 spin_unlock_bh(&jme->phy_lock);
2605 jme_reset_link(jme);
2606 jme->old_cmd = *cmd;
2607 set_bit(JME_FLAG_SSET, &jme->flags);
2617 struct jme_adapter *jme = netdev_priv(netdev);
2628 spin_lock_bh(&jme->phy_lock);
2629 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2630 spin_unlock_bh(&jme->phy_lock);
2634 jme_reset_link(jme);
2635 jme_get_link_ksettings(netdev, &jme->old_cmd);
2636 set_bit(JME_FLAG_SSET, &jme->flags);
2645 struct jme_adapter *jme = netdev_priv(netdev);
2646 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2652 struct jme_adapter *jme = netdev_priv(netdev);
2653 return jme->msg_enable;
2659 struct jme_adapter *jme = netdev_priv(netdev);
2660 jme->msg_enable = value;
2674 struct jme_adapter *jme = netdev_priv(netdev);
2676 spin_lock_bh(&jme->rxmcs_lock);
2678 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2680 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2681 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2682 spin_unlock_bh(&jme->rxmcs_lock);
2701 struct jme_adapter *jme = netdev_priv(netdev);
2702 jme_restart_an(jme);
2707 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2712 val = jread32(jme, JME_SMBCSR);
2716 val = jread32(jme, JME_SMBCSR);
2719 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2723 jwrite32(jme, JME_SMBINTF,
2728 val = jread32(jme, JME_SMBINTF);
2732 val = jread32(jme, JME_SMBINTF);
2735 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2743 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2748 val = jread32(jme, JME_SMBCSR);
2752 val = jread32(jme, JME_SMBCSR);
2755 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2759 jwrite32(jme, JME_SMBINTF,
2765 val = jread32(jme, JME_SMBINTF);
2769 val = jread32(jme, JME_SMBINTF);
2772 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2782 struct jme_adapter *jme = netdev_priv(netdev);
2784 val = jread32(jme, JME_SMBCSR);
2792 struct jme_adapter *jme = netdev_priv(netdev);
2800 data[i] = jme_smb_read(jme, i + offset);
2809 struct jme_adapter *jme = netdev_priv(netdev);
2819 jme_smb_write(jme, i + offset, data[i]);
2866 jme_phy_init(struct jme_adapter *jme)
2870 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2871 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2875 jme_check_hw_ver(struct jme_adapter *jme)
2879 chipmode = jread32(jme, JME_CHIPMODE);
2881 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2882 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2883 jme->chip_main_rev = jme->chiprev & 0xF;
2884 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2910 struct jme_adapter *jme;
2950 netdev = alloc_etherdev(sizeof(*jme));
2984 jme = netdev_priv(netdev);
2985 jme->pdev = pdev;
2986 jme->dev = netdev;
2987 jme->jme_rx = netif_rx;
2988 jme->old_mtu = netdev->mtu = 1500;
2989 jme->phylink = 0;
2990 jme->tx_ring_size = 1 << 10;
2991 jme->tx_ring_mask = jme->tx_ring_size - 1;
2992 jme->tx_wake_threshold = 1 << 9;
2993 jme->rx_ring_size = 1 << 9;
2994 jme->rx_ring_mask = jme->rx_ring_size - 1;
2995 jme->msg_enable = JME_DEF_MSG_ENABLE;
2996 jme->regs = ioremap(pci_resource_start(pdev, 0),
2998 if (!(jme->regs)) {
3005 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3006 jwrite32(jme, JME_APMC, apmc);
3008 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3009 jwrite32(jme, JME_APMC, apmc);
3012 netif_napi_add(netdev, &jme->napi, jme_poll);
3014 spin_lock_init(&jme->phy_lock);
3015 spin_lock_init(&jme->macaddr_lock);
3016 spin_lock_init(&jme->rxmcs_lock);
3018 atomic_set(&jme->link_changing, 1);
3019 atomic_set(&jme->rx_cleaning, 1);
3020 atomic_set(&jme->tx_cleaning, 1);
3021 atomic_set(&jme->rx_empty, 1);
3023 tasklet_setup(&jme->pcc_task, jme_pcc_tasklet);
3024 INIT_WORK(&jme->linkch_task, jme_link_change_work);
3025 jme->dpi.cur = PCC_P1;
3027 jme->reg_ghc = 0;
3028 jme->reg_rxcs = RXCS_DEFAULT;
3029 jme->reg_rxmcs = RXMCS_DEFAULT;
3030 jme->reg_txpfc = 0;
3031 jme->reg_pmcs = PMCS_MFEN;
3032 jme->reg_gpreg1 = GPREG1_DEFAULT;
3034 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3040 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3041 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3042 switch (jme->mrrs) {
3044 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3047 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3050 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3057 jme_check_hw_ver(jme);
3058 jme->mii_if.dev = netdev;
3059 if (jme->fpgaver) {
3060 jme->mii_if.phy_id = 0;
3065 jme->mii_if.phy_id = i;
3070 if (!jme->mii_if.phy_id) {
3076 jme->reg_ghc |= GHC_LINK_POLL;
3078 jme->mii_if.phy_id = 1;
3081 jme->mii_if.supports_gmii = true;
3083 jme->mii_if.supports_gmii = false;
3084 jme->mii_if.phy_id_mask = 0x1F;
3085 jme->mii_if.reg_num_mask = 0x1F;
3086 jme->mii_if.mdio_read = jme_mdio_read;
3087 jme->mii_if.mdio_write = jme_mdio_write;
3089 jme_clear_pm_disable_wol(jme);
3092 jme_set_phyfifo_5level(jme);
3093 jme->pcirev = pdev->revision;
3094 if (!jme->fpgaver)
3095 jme_phy_init(jme);
3096 jme_phy_off(jme);
3101 jme_reset_mac_processor(jme);
3102 rc = jme_reload_eeprom(jme);
3120 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3121 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3123 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3125 (jme->fpgaver != 0) ? " (FPGA)" : "",
3126 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3127 jme->pcirev, netdev->dev_addr);
3132 iounmap(jme->regs);
3147 struct jme_adapter *jme = netdev_priv(netdev);
3150 iounmap(jme->regs);
3161 struct jme_adapter *jme = netdev_priv(netdev);
3163 jme_powersave_phy(jme);
3172 struct jme_adapter *jme = netdev_priv(netdev);
3177 atomic_dec(&jme->link_changing);
3181 jme_stop_irq(jme);
3183 tasklet_disable(&jme->txclean_task);
3184 tasklet_disable(&jme->rxclean_task);
3185 tasklet_disable(&jme->rxempty_task);
3188 if (test_bit(JME_FLAG_POLL, &jme->flags))
3189 jme_polling_mode(jme);
3191 jme_stop_pcc_timer(jme);
3192 jme_disable_rx_engine(jme);
3193 jme_disable_tx_engine(jme);
3194 jme_reset_mac_processor(jme);
3195 jme_free_rx_resources(jme);
3196 jme_free_tx_resources(jme);
3198 jme->phylink = 0;
3201 tasklet_enable(&jme->txclean_task);
3202 tasklet_enable(&jme->rxclean_task);
3203 tasklet_enable(&jme->rxempty_task);
3205 jme_powersave_phy(jme);
3214 struct jme_adapter *jme = netdev_priv(netdev);
3219 jme_clear_pm_disable_wol(jme);
3220 jme_phy_on(jme);
3221 if (test_bit(JME_FLAG_SSET, &jme->flags))
3222 jme_set_link_ksettings(netdev, &jme->old_cmd);
3224 jme_reset_phy_processor(jme);
3225 jme_phy_calibration(jme);
3226 jme_phy_setEA(jme);
3229 atomic_inc(&jme->link_changing);
3231 jme_reset_link(jme);
3233 jme_start_irq(jme);