Lines Matching defs:address
621 /* Set the base address for flash register access */
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
758 * @address: EMI address to program
759 * @data: pointer to value to read/write from/to the EMI address
764 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
769 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
784 * @addr: EMI address to program
785 * @data: value to be read from the EMI address
797 * @addr: EMI address to program
798 * @data: value to be written to the EMI address
1872 * e1000_rar_set_pch2lan - Set receive address register
1874 * @addr: pointer to the receive address
1875 * @index: receive address array register
1877 * Sets the receive address array register at index to the address passed
1878 * in by addr. For 82579, RAR[0] is the base address register that is to
1879 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1895 /* If MAC address zero, no need to set the AV bit */
1908 * next address into the SHRA register array.
1934 e_dbg("Failed to write receive address at index %d\n", index);
1943 * program. SHRA[0-10] are the shared receive address registers
1975 * e1000_rar_set_pch_lpt - Set receive address registers
1977 * @addr: pointer to the receive address
1978 * @index: receive address array register
1980 * Sets the receive address register array at index to the address passed
1981 * in by addr. For LPT, RAR[0] is the base address register that is to
1982 * contain the MAC address. SHRA[0-10] are the shared receive address
1998 /* If MAC address zero, no need to set the AV bit */
2044 e_dbg("Failed to write receive address at index %d\n", index);
2068 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2184 /* HW configures the SMBus address and LEDs when the
4523 /* Start with the base address, then add the sector offset. */
4553 * block into Flash Linear address field in Flash
4822 * - setup receive address registers
4842 /* Setup the receive address. */