Lines Matching defs:mal
3 * drivers/net/ethernet/ibm/emac/mal.c
34 int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac)
38 spin_lock_irqsave(&mal->lock, flags);
40 MAL_DBG(mal, "reg(%08x, %08x)" NL,
44 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
45 (mal->rx_chan_mask & commac->rx_chan_mask)) {
46 spin_unlock_irqrestore(&mal->lock, flags);
47 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
48 mal->index);
52 if (list_empty(&mal->list))
53 napi_enable(&mal->napi);
54 mal->tx_chan_mask |= commac->tx_chan_mask;
55 mal->rx_chan_mask |= commac->rx_chan_mask;
56 list_add(&commac->list, &mal->list);
58 spin_unlock_irqrestore(&mal->lock, flags);
63 void mal_unregister_commac(struct mal_instance *mal,
68 spin_lock_irqsave(&mal->lock, flags);
70 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
73 mal->tx_chan_mask &= ~commac->tx_chan_mask;
74 mal->rx_chan_mask &= ~commac->rx_chan_mask;
76 if (list_empty(&mal->list))
77 napi_disable(&mal->napi);
79 spin_unlock_irqrestore(&mal->lock, flags);
82 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
84 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
87 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
91 "mal%d: incorrect RX size %lu for the channel %d\n",
92 mal->index, size, channel);
96 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
100 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
102 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
107 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
109 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
110 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
113 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
117 spin_lock_irqsave(&mal->lock, flags);
119 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
121 set_mal_dcrn(mal, MAL_TXCASR,
122 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
124 spin_unlock_irqrestore(&mal->lock, flags);
127 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
129 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
131 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
134 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
146 spin_lock_irqsave(&mal->lock, flags);
148 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
150 set_mal_dcrn(mal, MAL_RXCASR,
151 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
153 spin_unlock_irqrestore(&mal->lock, flags);
156 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
166 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
168 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
171 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
175 spin_lock_irqsave(&mal->lock, flags);
177 MAL_DBG(mal, "poll_add(%p)" NL, commac);
182 list_add_tail(&commac->poll_list, &mal->poll_list);
184 spin_unlock_irqrestore(&mal->lock, flags);
187 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
191 spin_lock_irqsave(&mal->lock, flags);
193 MAL_DBG(mal, "poll_del(%p)" NL, commac);
197 spin_unlock_irqrestore(&mal->lock, flags);
201 static inline void mal_enable_eob_irq(struct mal_instance *mal)
203 MAL_DBG2(mal, "enable_irq" NL);
206 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
210 static inline void mal_disable_eob_irq(struct mal_instance *mal)
213 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
215 MAL_DBG2(mal, "disable_irq" NL);
220 struct mal_instance *mal = dev_instance;
222 u32 esr = get_mal_dcrn(mal, MAL_ESR);
225 set_mal_dcrn(mal, MAL_ESR, esr);
227 MAL_DBG(mal, "SERR %08x" NL, esr);
243 "mal%d: system error, "
245 mal->index, esr);
254 "mal%d: system error, OPB (ESR = 0x%08x)\n",
255 mal->index, esr);
260 static inline void mal_schedule_poll(struct mal_instance *mal)
262 if (likely(napi_schedule_prep(&mal->napi))) {
263 MAL_DBG2(mal, "schedule_poll" NL);
264 spin_lock(&mal->lock);
265 mal_disable_eob_irq(mal);
266 spin_unlock(&mal->lock);
267 __napi_schedule(&mal->napi);
269 MAL_DBG2(mal, "already in poll" NL);
274 struct mal_instance *mal = dev_instance;
276 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
278 MAL_DBG2(mal, "txeob %08x" NL, r);
280 mal_schedule_poll(mal);
281 set_mal_dcrn(mal, MAL_TXEOBISR, r);
284 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
294 struct mal_instance *mal = dev_instance;
296 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
298 MAL_DBG2(mal, "rxeob %08x" NL, r);
300 mal_schedule_poll(mal);
301 set_mal_dcrn(mal, MAL_RXEOBISR, r);
304 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
314 struct mal_instance *mal = dev_instance;
316 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
317 set_mal_dcrn(mal, MAL_TXDEIR, deir);
319 MAL_DBG(mal, "txde %08x" NL, deir);
323 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
324 mal->index, deir);
331 struct mal_instance *mal = dev_instance;
334 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
336 MAL_DBG(mal, "rxde %08x" NL, deir);
338 list_for_each(l, &mal->list) {
346 mal_schedule_poll(mal);
347 set_mal_dcrn(mal, MAL_RXDEIR, deir);
354 struct mal_instance *mal = dev_instance;
355 u32 esr = get_mal_dcrn(mal, MAL_ESR);
371 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
378 napi_synchronize(&mal->napi);
381 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
391 napi_schedule(&mal->napi);
396 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
401 MAL_DBG2(mal, "poll(%d)" NL, budget);
404 list_for_each(l, &mal->poll_list) {
415 list_for_each(l, &mal->poll_list) {
431 spin_lock_irqsave(&mal->lock, flags);
432 mal_enable_eob_irq(mal);
433 spin_unlock_irqrestore(&mal->lock, flags);
437 list_for_each(l, &mal->poll_list) {
444 MAL_DBG2(mal, "rotting packet" NL);
448 spin_lock_irqsave(&mal->lock, flags);
449 mal_disable_eob_irq(mal);
450 spin_unlock_irqrestore(&mal->lock, flags);
456 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
460 static void mal_reset(struct mal_instance *mal)
464 MAL_DBG(mal, "reset" NL);
466 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
469 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
473 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
476 int mal_get_regs_len(struct mal_instance *mal)
482 void *mal_dump_regs(struct mal_instance *mal, void *buf)
488 hdr->version = mal->version;
489 hdr->index = mal->index;
491 regs->tx_count = mal->num_tx_chans;
492 regs->rx_count = mal->num_rx_chans;
494 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
495 regs->esr = get_mal_dcrn(mal, MAL_ESR);
496 regs->ier = get_mal_dcrn(mal, MAL_IER);
497 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
498 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
499 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
500 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
501 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
502 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
503 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
504 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
507 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
510 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
511 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
518 struct mal_instance *mal;
527 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
528 if (!mal)
531 mal->index = index;
532 mal->ofdev = ofdev;
533 mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
535 MAL_DBG(mal, "probe" NL);
540 "mal%d: can't find MAL num-tx-chans property!\n",
545 mal->num_tx_chans = prop[0];
550 "mal%d: can't find MAL num-rx-chans property!\n",
555 mal->num_rx_chans = prop[0];
560 "mal%d: can't find DCR resource!\n", index);
564 mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
565 if (!DCR_MAP_OK(mal->dcr_host)) {
567 "mal%d: failed to map DCRs !\n", index);
575 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
585 mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
586 mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
587 mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
589 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
590 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
592 mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
593 mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
596 if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq ||
597 !mal->txde_irq || !mal->rxde_irq) {
599 "mal%d: failed to map interrupts !\n", index);
604 INIT_LIST_HEAD(&mal->poll_list);
605 INIT_LIST_HEAD(&mal->list);
606 spin_lock_init(&mal->lock);
608 init_dummy_netdev(&mal->dummy_dev);
610 netif_napi_add_weight(&mal->dummy_dev, &mal->napi, mal_poll,
614 mal_reset(mal);
617 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
627 set_mal_dcrn(mal, MAL_CFG, cfg);
630 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
631 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
634 (NUM_TX_BUFF * mal->num_tx_chans +
635 NUM_RX_BUFF * mal->num_rx_chans);
636 mal->bd_virt = dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
638 if (mal->bd_virt == NULL) {
643 for (i = 0; i < mal->num_tx_chans; ++i)
644 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
646 mal_tx_bd_offset(mal, i));
648 for (i = 0; i < mal->num_rx_chans; ++i)
649 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
651 mal_rx_bd_offset(mal, i));
653 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
663 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
666 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
669 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
672 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
675 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
680 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
683 mal_enable_eob_irq(mal);
687 mal->version, ofdev->dev.of_node,
688 mal->num_tx_chans, mal->num_rx_chans);
692 platform_set_drvdata(ofdev, mal);
697 free_irq(mal->rxde_irq, mal);
699 free_irq(mal->txeob_irq, mal);
701 free_irq(mal->txde_irq, mal);
703 free_irq(mal->serr_irq, mal);
705 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
707 dcr_unmap(mal->dcr_host, 0x100);
709 kfree(mal);
716 struct mal_instance *mal = platform_get_drvdata(ofdev);
718 MAL_DBG(mal, "remove" NL);
721 napi_disable(&mal->napi);
723 if (!list_empty(&mal->list))
726 "mal%d: commac list is not empty on remove!\n",
727 mal->index);
729 free_irq(mal->serr_irq, mal);
730 free_irq(mal->txde_irq, mal);
731 free_irq(mal->txeob_irq, mal);
732 free_irq(mal->rxde_irq, mal);
733 free_irq(mal->rxeob_irq, mal);
735 mal_reset(mal);
739 (NUM_TX_BUFF * mal->num_tx_chans +
740 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
741 mal->bd_dma);
742 kfree(mal);