Lines Matching refs:reg
38 u8 __iomem *vbase; /* mdio reg base address */
43 /* mdio reg */
87 /* peri subctrl reg */
95 static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value)
97 writel_relaxed(value, base + reg);
100 #define MDIO_WRITE_REG(a, reg, value) \
101 mdio_write_reg((a)->vbase, (reg), (value))
103 static u32 mdio_read_reg(u8 __iomem *base, u32 reg)
105 return readl_relaxed(base + reg);
116 static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift,
119 u32 origin = mdio_read_reg(base, reg);
122 mdio_write_reg(base, reg, origin);
125 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
126 mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
128 static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift)
132 origin = mdio_read_reg(base, reg);
136 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
137 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
139 #define MDIO_GET_REG_BIT(dev, reg, bit) \
140 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
221 u16 reg = (u16)(regnum & 0xffff);
228 dev_dbg(&bus->dev, "phy id=%d, reg=%#x, write data=%d\n",
229 phy_id, reg, data);
238 cmd_reg_cfg = reg;
263 u16 reg = (u16)(regnum & 0xffff);
270 dev_dbg(&bus->dev, "phy id=%d, devad=%d, reg=%#x, write data=%d\n",
271 phy_id, devad, reg, data);
280 /* config the cmd-reg to write addr*/
282 MDIO_ADDR_DATA_S, reg);
316 u16 reg = (u16)(regnum & 0xffff);
322 dev_dbg(&bus->dev, "phy id=%d, reg=%#x!\n", phy_id, reg);
331 hns_mdio_cmd_write(mdio_dev, false, MDIO_C22_READ, phy_id, reg);
367 u16 reg = (u16)(regnum & 0xffff);
373 dev_dbg(&bus->dev, "phy id=%d, devad=%d, reg=%#x!\n",
374 phy_id, devad, reg);
384 MDIO_ADDR_DATA_S, reg);
386 /* Step 2; config the cmd-reg to write addr*/
433 dev_err(&bus->dev, "mdio sys ctl reg has not mapped\n");