Lines Matching refs:regs

62 static u32 xgmac_read32(void __iomem *regs,
66 		return ioread32(regs);
68 		return ioread32be(regs);
72 			  void __iomem *regs,
76 		iowrite32(value, regs);
78 		iowrite32be(value, regs);
85 				 struct tgec_mdio_controller __iomem *regs,
92 	while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
110 				 struct tgec_mdio_controller __iomem *regs,
117 	while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
135 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
141 	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
143 	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
145 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
151 	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
154 	xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian);
156 	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
167 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
172 	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
175 	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
177 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
183 	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
186 	xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
188 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
193 	xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian);
195 	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
204  * TSEC1 MIIM regs.
209 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
217 	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
219 	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
221 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
227 	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
236 	xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian);
238 	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
243 	if ((xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
250 		ret = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
263  * TSEC1 MIIM regs.
269 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
275 	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
278 	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
280 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
286 	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
289 	xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
291 	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
302 	xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian);
304 	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
309 	if ((xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
316 		ret = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
330 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
349 	mdio_stat = xgmac_read32(&regs->mdio_stat, priv->is_little_endian);
352 	xgmac_write32(mdio_stat, &regs->mdio_stat, priv->is_little_endian);
359 	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
366 	mdio_stat = xgmac_read32(&regs->mdio_stat, priv->is_little_endian);
368 	xgmac_write32(mdio_stat, &regs->mdio_stat, priv->is_little_endian);