Lines Matching defs:ugeth
225 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
230 skb = netdev_alloc_skb(ugeth->ndev,
231 ugeth->ug_info->uf_info.max_rx_buf_length +
245 dma_map_single(ugeth->dev,
247 ugeth->ug_info->uf_info.max_rx_buf_length +
257 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
264 bd = ugeth->p_rx_bd_ring[rxQ];
269 skb = get_new_skb(ugeth, bd);
275 ugeth->rx_skbuff[rxQ][i] = skb;
285 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
299 if (netif_msg_ifup(ugeth))
310 if (netif_msg_ifup(ugeth))
324 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
358 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
410 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
420 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
432 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
439 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
443 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
456 static void get_statistics(struct ucc_geth_private *ugeth,
468 ug_regs = ugeth->ug_regs;
470 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
471 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
576 static void dump_bds(struct ucc_geth_private *ugeth)
581 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) {
582 if (ugeth->p_tx_bd_ring[i]) {
584 (ugeth->ug_info->bdRingLenTx[i] *
587 mem_disp(ugeth->p_tx_bd_ring[i], length);
590 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
591 if (ugeth->p_rx_bd_ring[i]) {
593 (ugeth->ug_info->bdRingLenRx[i] *
596 mem_disp(ugeth->p_rx_bd_ring[i], length);
601 static void dump_regs(struct ucc_geth_private *ugeth)
605 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
606 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
609 (u32)&ugeth->ug_regs->maccfg1,
610 in_be32(&ugeth->ug_regs->maccfg1));
612 (u32)&ugeth->ug_regs->maccfg2,
613 in_be32(&ugeth->ug_regs->maccfg2));
615 (u32)&ugeth->ug_regs->ipgifg,
616 in_be32(&ugeth->ug_regs->ipgifg));
618 (u32)&ugeth->ug_regs->hafdup,
619 in_be32(&ugeth->ug_regs->hafdup));
621 (u32)&ugeth->ug_regs->ifctl,
622 in_be32(&ugeth->ug_regs->ifctl));
624 (u32)&ugeth->ug_regs->ifstat,
625 in_be32(&ugeth->ug_regs->ifstat));
627 (u32)&ugeth->ug_regs->macstnaddr1,
628 in_be32(&ugeth->ug_regs->macstnaddr1));
630 (u32)&ugeth->ug_regs->macstnaddr2,
631 in_be32(&ugeth->ug_regs->macstnaddr2));
633 (u32)&ugeth->ug_regs->uempr,
634 in_be32(&ugeth->ug_regs->uempr));
636 (u32)&ugeth->ug_regs->utbipar,
637 in_be32(&ugeth->ug_regs->utbipar));
639 (u32)&ugeth->ug_regs->uescr,
640 in_be16(&ugeth->ug_regs->uescr));
642 (u32)&ugeth->ug_regs->tx64,
643 in_be32(&ugeth->ug_regs->tx64));
645 (u32)&ugeth->ug_regs->tx127,
646 in_be32(&ugeth->ug_regs->tx127));
648 (u32)&ugeth->ug_regs->tx255,
649 in_be32(&ugeth->ug_regs->tx255));
651 (u32)&ugeth->ug_regs->rx64,
652 in_be32(&ugeth->ug_regs->rx64));
654 (u32)&ugeth->ug_regs->rx127,
655 in_be32(&ugeth->ug_regs->rx127));
657 (u32)&ugeth->ug_regs->rx255,
658 in_be32(&ugeth->ug_regs->rx255));
660 (u32)&ugeth->ug_regs->txok,
661 in_be32(&ugeth->ug_regs->txok));
663 (u32)&ugeth->ug_regs->txcf,
664 in_be16(&ugeth->ug_regs->txcf));
666 (u32)&ugeth->ug_regs->tmca,
667 in_be32(&ugeth->ug_regs->tmca));
669 (u32)&ugeth->ug_regs->tbca,
670 in_be32(&ugeth->ug_regs->tbca));
672 (u32)&ugeth->ug_regs->rxfok,
673 in_be32(&ugeth->ug_regs->rxfok));
675 (u32)&ugeth->ug_regs->rxbok,
676 in_be32(&ugeth->ug_regs->rxbok));
678 (u32)&ugeth->ug_regs->rbyt,
679 in_be32(&ugeth->ug_regs->rbyt));
681 (u32)&ugeth->ug_regs->rmca,
682 in_be32(&ugeth->ug_regs->rmca));
684 (u32)&ugeth->ug_regs->rbca,
685 in_be32(&ugeth->ug_regs->rbca));
687 (u32)&ugeth->ug_regs->scar,
688 in_be32(&ugeth->ug_regs->scar));
690 (u32)&ugeth->ug_regs->scam,
691 in_be32(&ugeth->ug_regs->scam));
693 if (ugeth->p_thread_data_tx) {
694 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsTx);
698 (u32)ugeth->p_thread_data_tx);
702 (u32)&ugeth->p_thread_data_tx[i]);
703 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
707 if (ugeth->p_thread_data_rx) {
708 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsRx);
712 (u32)ugeth->p_thread_data_rx);
716 (u32)&ugeth->p_thread_data_rx[i]);
717 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
721 if (ugeth->p_exf_glbl_param) {
724 (u32)ugeth->p_exf_glbl_param);
725 mem_disp((u8 *) ugeth->p_exf_glbl_param,
726 sizeof(*ugeth->p_exf_glbl_param));
728 if (ugeth->p_tx_glbl_pram) {
730 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
732 (u32)&ugeth->p_tx_glbl_pram->temoder,
733 in_be16(&ugeth->p_tx_glbl_pram->temoder));
735 (u32)&ugeth->p_tx_glbl_pram->sqptr,
736 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
738 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
739 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
741 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
742 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
744 (u32)&ugeth->p_tx_glbl_pram->tstate,
745 in_be32(&ugeth->p_tx_glbl_pram->tstate));
747 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
748 ugeth->p_tx_glbl_pram->iphoffset[0]);
750 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
751 ugeth->p_tx_glbl_pram->iphoffset[1]);
753 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
754 ugeth->p_tx_glbl_pram->iphoffset[2]);
756 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
757 ugeth->p_tx_glbl_pram->iphoffset[3]);
759 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
760 ugeth->p_tx_glbl_pram->iphoffset[4]);
762 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
763 ugeth->p_tx_glbl_pram->iphoffset[5]);
765 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
766 ugeth->p_tx_glbl_pram->iphoffset[6]);
768 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
769 ugeth->p_tx_glbl_pram->iphoffset[7]);
771 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
772 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
774 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
775 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
777 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
778 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
780 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
781 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
783 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
784 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
786 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
787 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
789 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
790 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
792 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
793 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
795 (u32)&ugeth->p_tx_glbl_pram->tqptr,
796 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
798 if (ugeth->p_rx_glbl_pram) {
800 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
802 (u32)&ugeth->p_rx_glbl_pram->remoder,
803 in_be32(&ugeth->p_rx_glbl_pram->remoder));
805 (u32)&ugeth->p_rx_glbl_pram->rqptr,
806 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
808 (u32)&ugeth->p_rx_glbl_pram->typeorlen,
809 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
811 (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
812 ugeth->p_rx_glbl_pram->rxgstpack);
814 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
815 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
817 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
818 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
820 (u32)&ugeth->p_rx_glbl_pram->rstate,
821 ugeth->p_rx_glbl_pram->rstate);
823 (u32)&ugeth->p_rx_glbl_pram->mrblr,
824 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
826 (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
827 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
829 (u32)&ugeth->p_rx_glbl_pram->mflr,
830 in_be16(&ugeth->p_rx_glbl_pram->mflr));
832 (u32)&ugeth->p_rx_glbl_pram->minflr,
833 in_be16(&ugeth->p_rx_glbl_pram->minflr));
835 (u32)&ugeth->p_rx_glbl_pram->maxd1,
836 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
838 (u32)&ugeth->p_rx_glbl_pram->maxd2,
839 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
841 (u32)&ugeth->p_rx_glbl_pram->ecamptr,
842 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
844 (u32)&ugeth->p_rx_glbl_pram->l2qt,
845 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
847 (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
848 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
850 (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
851 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
853 (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
854 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
856 (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
857 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
859 (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
860 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
862 (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
863 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
865 (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
866 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
868 (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
869 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
871 (u32)&ugeth->p_rx_glbl_pram->vlantype,
872 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
874 (u32)&ugeth->p_rx_glbl_pram->vlantci,
875 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
879 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
880 ugeth->p_rx_glbl_pram->addressfiltering[i]);
882 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
883 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
885 if (ugeth->p_send_q_mem_reg) {
887 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
888 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) {
891 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
892 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
896 if (ugeth->p_scheduler) {
898 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
899 mem_disp((u8 *) ugeth->p_scheduler,
900 sizeof(*ugeth->p_scheduler));
902 if (ugeth->p_tx_fw_statistics_pram) {
905 (u32)ugeth->p_tx_fw_statistics_pram);
906 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
907 sizeof(*ugeth->p_tx_fw_statistics_pram));
909 if (ugeth->p_rx_fw_statistics_pram) {
912 (u32)ugeth->p_rx_fw_statistics_pram);
913 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
914 sizeof(*ugeth->p_rx_fw_statistics_pram));
916 if (ugeth->p_rx_irq_coalescing_tbl) {
919 (u32)ugeth->p_rx_irq_coalescing_tbl);
920 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
923 (u32)&ugeth->p_rx_irq_coalescing_tbl->
926 (u32)&ugeth->p_rx_irq_coalescing_tbl->
928 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
932 (u32)&ugeth->p_rx_irq_coalescing_tbl->
934 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
939 if (ugeth->p_rx_bd_qs_tbl) {
941 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
942 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
945 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
947 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
948 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
950 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
951 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
953 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
954 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
957 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
958 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
962 (&ugeth->p_rx_bd_qs_tbl[i].
966 (&ugeth->p_rx_bd_qs_tbl[i].
971 if (ugeth->p_init_enet_param_shadow) {
975 (u32) ugeth->p_init_enet_param_shadow);
976 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
977 sizeof(*ugeth->p_init_enet_param_shadow));
980 if (ugeth->ug_info->rxExtendedFiltering) {
983 if (ugeth->ug_info->largestexternallookupkeysize ==
987 if (ugeth->ug_info->largestexternallookupkeysize ==
993 dump_init_enet_entries(ugeth,
994 &(ugeth->p_init_enet_param_shadow->
998 ugeth->ug_info->riscTx, 0);
999 dump_init_enet_entries(ugeth,
1000 &(ugeth->p_init_enet_param_shadow->
1003 ugeth->ug_info->riscRx, 1);
1290 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1301 ug_info = ugeth->ug_info;
1302 ug_regs = ugeth->ug_regs;
1303 uf_regs = ugeth->uccf->uf_regs;
1308 if ((ugeth->max_speed == SPEED_10) ||
1309 (ugeth->max_speed == SPEED_100))
1311 else if (ugeth->max_speed == SPEED_1000)
1320 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1321 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1322 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1323 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1324 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1325 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1326 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1328 switch (ugeth->max_speed) {
1333 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1337 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1338 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1341 if (ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)
1349 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1350 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1351 struct ucc_geth_info *ug_info = ugeth->ug_info;
1372 if (netif_msg_probe(ugeth))
1380 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1387 uccf = ugeth->uccf;
1395 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1410 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1417 uccf = ugeth->uccf;
1420 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1422 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1429 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1434 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1442 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1447 uccf = ugeth->uccf;
1450 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1457 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1462 uccf = ugeth->uccf;
1465 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1473 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1478 uccf = ugeth->uccf;
1481 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1482 if (netif_msg_probe(ugeth))
1493 ugeth_restart_tx(ugeth);
1495 ugeth_restart_rx(ugeth);
1503 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1507 uccf = ugeth->uccf;
1510 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1511 if (netif_msg_probe(ugeth))
1518 ugeth_graceful_stop_tx(ugeth);
1522 ugeth_graceful_stop_rx(ugeth);
1524 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1529 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1532 netif_tx_stop_all_queues(ugeth->ndev);
1535 disable_irq(ugeth->ug_info->uf_info.irq);
1538 napi_disable(&ugeth->napi);
1541 static void ugeth_activate(struct ucc_geth_private *ugeth)
1543 napi_enable(&ugeth->napi);
1544 enable_irq(ugeth->ug_info->uf_info.irq);
1547 netif_tx_wake_all_queues(ugeth->ndev);
1548 __netdev_watchdog_up(ugeth->ndev);
1553 * information through variables in the ugeth structure, and this
1560 struct ucc_geth_private *ugeth = netdev_priv(dev);
1563 struct phy_device *phydev = ugeth->phydev;
1566 ug_regs = ugeth->ug_regs;
1567 uf_regs = ugeth->uccf->uf_regs;
1574 if (phydev->duplex != ugeth->oldduplex) {
1580 ugeth->oldduplex = phydev->duplex;
1583 if (phydev->speed != ugeth->oldspeed) {
1597 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1598 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1599 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1600 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1601 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1602 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1610 if (netif_msg_link(ugeth))
1616 ugeth->oldspeed = phydev->speed;
1619 if (!ugeth->oldlink) {
1621 ugeth->oldlink = 1;
1628 * ugeth->lock, which is a bad idea since 'graceful
1632 ugeth_quiesce(ugeth);
1633 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1638 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1639 ugeth_activate(ugeth);
1641 } else if (ugeth->oldlink) {
1643 ugeth->oldlink = 0;
1644 ugeth->oldspeed = 0;
1645 ugeth->oldduplex = -1;
1648 if (new_state && netif_msg_link(ugeth))
1662 struct ucc_geth_private *ugeth = netdev_priv(dev);
1663 struct ucc_geth_info *ug_info = ugeth->ug_info;
1729 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1732 ucc_fast_dump_regs(ugeth->uccf);
1733 dump_regs(ugeth);
1734 dump_bds(ugeth);
1739 ugeth,
1752 uccf = ugeth->uccf;
1756 ugeth->p_rx_glbl_pram->addressfiltering;
1761 p_lh = &ugeth->group_hash_q;
1762 p_counter = &(ugeth->numGroupAddrInHash);
1766 p_lh = &ugeth->ind_hash_q;
1767 p_counter = &(ugeth->numIndAddrInHash);
1777 ugeth_disable(ugeth, comm_dir);
1795 ugeth_enable(ugeth, comm_dir);
1800 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1803 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1804 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1807 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1815 ug_info = ugeth->ug_info;
1818 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
1819 if (ugeth->p_rx_bd_ring[i]) {
1821 bd = ugeth->p_rx_bd_ring[i];
1822 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1823 if (ugeth->rx_skbuff[i][j]) {
1824 dma_unmap_single(ugeth->dev,
1826 ugeth->ug_info->
1831 ugeth->rx_skbuff[i][j]);
1832 ugeth->rx_skbuff[i][j] = NULL;
1837 kfree(ugeth->rx_skbuff[i]);
1839 kfree(ugeth->p_rx_bd_ring[i]);
1840 ugeth->p_rx_bd_ring[i] = NULL;
1846 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1853 netdev_reset_queue(ugeth->ndev);
1855 ug_info = ugeth->ug_info;
1858 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) {
1859 bd = ugeth->p_tx_bd_ring[i];
1862 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1863 if (ugeth->tx_skbuff[i][j]) {
1864 dma_unmap_single(ugeth->dev,
1869 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1870 ugeth->tx_skbuff[i][j] = NULL;
1874 kfree(ugeth->tx_skbuff[i]);
1876 kfree(ugeth->p_tx_bd_ring[i]);
1877 ugeth->p_tx_bd_ring[i] = NULL;
1882 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1884 if (!ugeth)
1887 if (ugeth->uccf) {
1888 ucc_fast_free(ugeth->uccf);
1889 ugeth->uccf = NULL;
1892 qe_muram_free_addr(ugeth->p_thread_data_tx);
1893 ugeth->p_thread_data_tx = NULL;
1895 qe_muram_free_addr(ugeth->p_thread_data_rx);
1896 ugeth->p_thread_data_rx = NULL;
1898 qe_muram_free_addr(ugeth->p_exf_glbl_param);
1899 ugeth->p_exf_glbl_param = NULL;
1901 qe_muram_free_addr(ugeth->p_rx_glbl_pram);
1902 ugeth->p_rx_glbl_pram = NULL;
1904 qe_muram_free_addr(ugeth->p_tx_glbl_pram);
1905 ugeth->p_tx_glbl_pram = NULL;
1907 qe_muram_free_addr(ugeth->p_send_q_mem_reg);
1908 ugeth->p_send_q_mem_reg = NULL;
1910 qe_muram_free_addr(ugeth->p_scheduler);
1911 ugeth->p_scheduler = NULL;
1913 qe_muram_free_addr(ugeth->p_tx_fw_statistics_pram);
1914 ugeth->p_tx_fw_statistics_pram = NULL;
1916 qe_muram_free_addr(ugeth->p_rx_fw_statistics_pram);
1917 ugeth->p_rx_fw_statistics_pram = NULL;
1919 qe_muram_free_addr(ugeth->p_rx_irq_coalescing_tbl);
1920 ugeth->p_rx_irq_coalescing_tbl = NULL;
1922 qe_muram_free_addr(ugeth->p_rx_bd_qs_tbl);
1923 ugeth->p_rx_bd_qs_tbl = NULL;
1925 if (ugeth->p_init_enet_param_shadow) {
1926 return_init_enet_entries(ugeth,
1927 &(ugeth->p_init_enet_param_shadow->
1930 ugeth->ug_info->riscRx, 1);
1931 return_init_enet_entries(ugeth,
1932 &(ugeth->p_init_enet_param_shadow->
1935 ugeth->ug_info->riscTx, 0);
1936 kfree(ugeth->p_init_enet_param_shadow);
1937 ugeth->p_init_enet_param_shadow = NULL;
1939 ucc_geth_free_tx(ugeth);
1940 ucc_geth_free_rx(ugeth);
1941 while (!list_empty(&ugeth->group_hash_q))
1943 (dequeue(&ugeth->group_hash_q)));
1944 while (!list_empty(&ugeth->ind_hash_q))
1946 (dequeue(&ugeth->ind_hash_q)));
1947 if (ugeth->ug_regs) {
1948 iounmap(ugeth->ug_regs);
1949 ugeth->ug_regs = NULL;
1955 struct ucc_geth_private *ugeth;
1960 ugeth = netdev_priv(dev);
1962 uf_regs = ugeth->uccf->uf_regs;
1970 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1989 hw_add_addr_in_hash(ugeth, ha->addr);
1995 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
1997 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
1998 struct phy_device *phydev = ugeth->phydev;
2010 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2013 out_be32(ugeth->uccf->p_uccm, 0x00000000);
2016 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2021 ucc_geth_memclean(ugeth);
2024 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2030 ug_info = ugeth->ug_info;
2038 if (netif_msg_probe(ugeth))
2047 if (netif_msg_probe(ugeth))
2056 if (netif_msg_probe(ugeth))
2063 if (netif_msg_probe(ugeth))
2070 if (netif_msg_probe(ugeth))
2078 if (netif_msg_probe(ugeth))
2087 if (netif_msg_probe(ugeth))
2094 if (netif_msg_probe(ugeth))
2102 if (netif_msg_probe(ugeth))
2115 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2116 if (netif_msg_probe(ugeth))
2129 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2130 if (!ugeth->ug_regs) {
2131 if (netif_msg_probe(ugeth))
2139 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2147 ug_info = ugeth->ug_info;
2160 ugeth->p_tx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL);
2162 if (!ugeth->p_tx_bd_ring[j]) {
2163 if (netif_msg_ifup(ugeth))
2168 memset(ugeth->p_tx_bd_ring[j] + length, 0, alloc - length);
2174 ugeth->tx_skbuff[j] =
2175 kcalloc(ugeth->ug_info->bdRingLenTx[j],
2178 if (ugeth->tx_skbuff[j] == NULL) {
2179 if (netif_msg_ifup(ugeth))
2184 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2185 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2201 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2209 ug_info = ugeth->ug_info;
2221 ugeth->p_rx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL);
2222 if (!ugeth->p_rx_bd_ring[j]) {
2223 if (netif_msg_ifup(ugeth))
2232 ugeth->rx_skbuff[j] =
2233 kcalloc(ugeth->ug_info->bdRingLenRx[j],
2236 if (ugeth->rx_skbuff[j] == NULL) {
2237 if (netif_msg_ifup(ugeth))
2242 ugeth->skb_currx[j] = 0;
2243 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2259 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2279 uccf = ugeth->uccf;
2280 ug_info = ugeth->ug_info;
2283 ug_regs = ugeth->ug_regs;
2287 if (netif_msg_ifup(ugeth))
2294 if (netif_msg_ifup(ugeth))
2300 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2305 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2342 if (netif_msg_ifup(ugeth))
2358 if (netif_msg_ifup(ugeth))
2378 ret_val = ucc_geth_alloc_tx(ugeth);
2382 ret_val = ucc_geth_alloc_rx(ugeth);
2395 if (netif_msg_ifup(ugeth))
2399 ugeth->p_tx_glbl_pram = qe_muram_addr(tx_glbl_pram_offset);
2404 ugeth->thread_dat_tx_offset =
2409 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2410 if (netif_msg_ifup(ugeth))
2415 ugeth->p_thread_data_tx =
2416 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2418 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2422 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2427 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2432 ugeth->send_q_mem_reg_offset =
2436 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2437 if (netif_msg_ifup(ugeth))
2442 ugeth->p_send_q_mem_reg =
2443 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2445 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2451 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2453 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2454 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2455 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2464 ugeth->scheduler_offset =
2467 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2468 if (netif_msg_ifup(ugeth))
2473 ugeth->p_scheduler =
2474 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2476 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2477 ugeth->scheduler_offset);
2480 out_be32(&ugeth->p_scheduler->mblinterval,
2482 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2484 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2485 out_8(&ugeth->p_scheduler->strictpriorityq,
2487 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2488 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2490 out_8(&ugeth->p_scheduler->weightfactor[i],
2494 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2495 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2496 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2497 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2498 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2499 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2500 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2501 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2508 ugeth->tx_fw_statistics_pram_offset =
2512 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2513 if (netif_msg_ifup(ugeth))
2517 ugeth->p_tx_fw_statistics_pram =
2519 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2530 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2537 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2545 if (netif_msg_ifup(ugeth))
2549 ugeth->p_rx_glbl_pram = qe_muram_addr(rx_glbl_pram_offset);
2554 ugeth->thread_dat_rx_offset =
2558 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2559 if (netif_msg_ifup(ugeth))
2564 ugeth->p_thread_data_rx =
2565 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2567 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2570 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2575 ugeth->rx_fw_statistics_pram_offset =
2579 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2580 if (netif_msg_ifup(ugeth))
2584 ugeth->p_rx_fw_statistics_pram =
2586 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2592 ugeth->rx_irq_coalescing_tbl_offset =
2596 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2597 if (netif_msg_ifup(ugeth))
2602 ugeth->p_rx_irq_coalescing_tbl =
2604 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2605 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2606 ugeth->rx_irq_coalescing_tbl_offset);
2610 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2613 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2620 &ugeth->p_rx_glbl_pram->mrblr);
2622 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2625 &ugeth->p_rx_glbl_pram->minflr,
2626 &ugeth->p_rx_glbl_pram->mrblr);
2628 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2630 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2636 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2643 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2647 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2650 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2653 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2657 ugeth->rx_bd_qs_tbl_offset =
2662 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2663 if (netif_msg_ifup(ugeth))
2668 ugeth->p_rx_bd_qs_tbl =
2669 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2671 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2676 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2677 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2684 if (ugeth->rx_extended_features)
2703 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2713 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2714 ugeth->tx_fw_statistics_pram_offset,
2715 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2716 ugeth->rx_fw_statistics_pram_offset,
2717 &ugeth->p_tx_glbl_pram->temoder,
2718 &ugeth->p_rx_glbl_pram->remoder);
2721 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2726 if (netif_msg_ifup(ugeth))
2733 ugeth->exf_glbl_param_offset =
2736 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2737 if (netif_msg_ifup(ugeth))
2742 ugeth->p_exf_glbl_param =
2743 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2745 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2746 ugeth->exf_glbl_param_offset);
2747 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2755 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2758 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2761 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2763 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2780 if (!(ugeth->p_init_enet_param_shadow =
2782 if (netif_msg_ifup(ugeth))
2789 ugeth->p_init_enet_param_shadow->resinit1 =
2791 ugeth->p_init_enet_param_shadow->resinit2 =
2793 ugeth->p_init_enet_param_shadow->resinit3 =
2795 ugeth->p_init_enet_param_shadow->resinit4 =
2797 ugeth->p_init_enet_param_shadow->resinit5 =
2799 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2801 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2804 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2812 if (netif_msg_ifup(ugeth))
2816 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2831 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2837 if (netif_msg_ifup(ugeth))
2842 ugeth->p_init_enet_param_shadow->txglobal =
2845 fill_init_enet_entries(ugeth,
2846 &(ugeth->p_init_enet_param_shadow->
2851 if (netif_msg_ifup(ugeth))
2858 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
2859 if (netif_msg_ifup(ugeth))
2868 if (netif_msg_ifup(ugeth))
2877 ugeth->p_init_enet_param_shadow->resinit1);
2879 ugeth->p_init_enet_param_shadow->resinit2);
2881 ugeth->p_init_enet_param_shadow->resinit3);
2883 ugeth->p_init_enet_param_shadow->resinit4);
2885 ugeth->p_init_enet_param_shadow->resinit5);
2887 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
2889 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
2892 ugeth->p_init_enet_param_shadow->rxthread[i]);
2894 ugeth->p_init_enet_param_shadow->txglobal);
2897 ugeth->p_init_enet_param_shadow->txthread[i]);
2901 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
2916 struct ucc_geth_private *ugeth = netdev_priv(dev);
2928 spin_lock_irqsave(&ugeth->lock, flags);
2933 bd = ugeth->txBd[txQ];
2936 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
2939 ugeth->skb_curtx[txQ] =
2940 (ugeth->skb_curtx[txQ] +
2941 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
2945 dma_map_single(ugeth->dev, skb->data,
2959 bd = ugeth->p_tx_bd_ring[txQ];
2963 if (bd == ugeth->confBd[txQ]) {
2968 ugeth->txBd[txQ] = bd;
2972 if (ugeth->p_scheduler) {
2973 ugeth->cpucount[txQ]++;
2978 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
2982 uccf = ugeth->uccf;
2985 spin_unlock_irqrestore(&ugeth->lock, flags);
2990 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3001 dev = ugeth->ndev;
3004 bd = ugeth->rxBd[rxQ];
3012 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3019 if (netif_msg_rx_err(ugeth))
3024 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3034 skb->protocol = eth_type_trans(skb, ugeth->ndev);
3041 skb = get_new_skb(ugeth, bd);
3043 if (netif_msg_rx_err(ugeth))
3049 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3052 ugeth->skb_currx[rxQ] =
3053 (ugeth->skb_currx[rxQ] +
3054 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3057 bd = ugeth->p_rx_bd_ring[rxQ];
3064 ugeth->rxBd[rxQ] = bd;
3071 struct ucc_geth_private *ugeth = netdev_priv(dev);
3077 bd = ugeth->confBd[txQ];
3088 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3097 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3098 ugeth->skb_dirtytx[txQ] =
3099 (ugeth->skb_dirtytx[txQ] +
3100 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3110 bd = ugeth->p_tx_bd_ring[txQ];
3113 ugeth->confBd[txQ] = bd;
3120 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3124 ug_info = ugeth->ug_info;
3127 spin_lock(&ugeth->lock);
3129 ucc_geth_tx(ugeth->ndev, i);
3130 spin_unlock(&ugeth->lock);
3134 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3138 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3147 struct ucc_geth_private *ugeth = netdev_priv(dev);
3155 uccf = ugeth->uccf;
3156 ug_info = ugeth->ug_info;
3166 if (napi_schedule_prep(&ugeth->napi)) {
3169 __napi_schedule(&ugeth->napi);
3192 struct ucc_geth_private *ugeth = netdev_priv(dev);
3193 int irq = ugeth->ug_info->uf_info.irq;
3203 struct ucc_geth_private *ugeth = netdev_priv(dev);
3218 spin_lock_irq(&ugeth->lock);
3225 &ugeth->ug_regs->macstnaddr1,
3226 &ugeth->ug_regs->macstnaddr2);
3227 spin_unlock_irq(&ugeth->lock);
3232 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3234 struct net_device *dev = ugeth->ndev;
3237 err = ucc_struct_init(ugeth);
3239 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3243 err = ucc_geth_startup(ugeth);
3245 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3249 err = adjust_enet_interface(ugeth);
3251 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3263 &ugeth->ug_regs->macstnaddr1,
3264 &ugeth->ug_regs->macstnaddr2);
3266 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3268 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3274 ucc_geth_stop(ugeth);
3282 struct ucc_geth_private *ugeth = netdev_priv(dev);
3289 netif_err(ugeth, ifup, dev,
3296 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3300 err = ucc_geth_init_mac(ugeth);
3302 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3306 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3309 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3313 phy_start(ugeth->phydev);
3314 napi_enable(&ugeth->napi);
3319 qe_alive_during_sleep() || ugeth->phydev->irq);
3320 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3325 ucc_geth_stop(ugeth);
3332 struct ucc_geth_private *ugeth = netdev_priv(dev);
3336 napi_disable(&ugeth->napi);
3338 cancel_work_sync(&ugeth->timeout_work);
3339 ucc_geth_stop(ugeth);
3340 phy_disconnect(ugeth->phydev);
3341 ugeth->phydev = NULL;
3343 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3354 struct ucc_geth_private *ugeth;
3357 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3358 dev = ugeth->ndev;
3364 ugeth_dump_regs(ugeth);
3372 ucc_geth_stop(ugeth);
3373 ucc_geth_init_mac(ugeth);
3375 phy_start(ugeth->phydev);
3388 struct ucc_geth_private *ugeth = netdev_priv(dev);
3390 schedule_work(&ugeth->timeout_work);
3399 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3405 napi_disable(&ugeth->napi);
3411 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3413 if (ugeth->wol_en & WAKE_MAGIC) {
3414 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3415 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3416 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3417 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3418 phy_stop(ugeth->phydev);
3427 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3434 if (ugeth->wol_en & WAKE_MAGIC) {
3435 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3436 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3437 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3439 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3445 ucc_geth_memclean(ugeth);
3447 err = ucc_geth_init_mac(ugeth);
3454 ugeth->oldlink = 0;
3455 ugeth->oldspeed = 0;
3456 ugeth->oldduplex = -1;
3458 phy_stop(ugeth->phydev);
3459 phy_start(ugeth->phydev);
3461 napi_enable(&ugeth->napi);
3500 struct ucc_geth_private *ugeth = netdev_priv(dev);
3505 if (!ugeth->phydev)
3508 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3561 struct ucc_geth_private *ugeth = NULL;
3690 dev = alloc_etherdev(sizeof(*ugeth));
3697 ugeth = netdev_priv(dev);
3698 spin_lock_init(&ugeth->lock);
3701 INIT_LIST_HEAD(&ugeth->group_hash_q);
3702 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3715 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3716 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll);
3720 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3721 ugeth->phy_interface = phy_interface;
3722 ugeth->max_speed = max_speed;
3729 if (netif_msg_probe(ugeth))
3737 ugeth->ug_info = ug_info;
3738 ugeth->dev = device;
3739 ugeth->ndev = dev;
3740 ugeth->node = np;
3760 struct ucc_geth_private *ugeth = netdev_priv(dev);
3764 ucc_geth_memclean(ugeth);
3767 of_node_put(ugeth->ug_info->tbi_node);
3768 of_node_put(ugeth->ug_info->phy_node);
3769 kfree(ugeth->ug_info);