Lines Matching refs:reg
35 #define FEC_IEVENT 0x004 /* Interrupt event reg */
36 #define FEC_IMASK 0x008 /* Interrupt mask reg */
37 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
38 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
39 #define FEC_ECNTRL 0x024 /* Ethernet control reg */
40 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
41 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
42 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
43 #define FEC_R_CNTRL 0x084 /* Receive control reg */
44 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
59 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
60 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
87 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
88 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
151 #define FEC_ECNTRL 0x000 /* Ethernet control reg */
152 #define FEC_IEVENT 0x004 /* Interrupt even reg */
153 #define FEC_IMASK 0x008 /* Interrupt mask reg */
154 #define FEC_IVEC 0x00c /* Interrupt vec status reg */
155 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
158 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
161 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
162 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
163 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
164 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */
166 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
167 #define FEC_R_CNTRL 0x104 /* Receive control reg */
168 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
169 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */
587 u8 reg;