Lines Matching defs:enable
819 /* enable UPD (update prepanded data) bit in FAEAD field of
1614 bool enable)
1618 err = dpni_enable_vlan_filter(priv->mc_io, 0, priv->mc_token, enable);
1629 static int dpaa2_eth_set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
1634 DPNI_OFF_RX_L3_CSUM, enable);
1642 DPNI_OFF_RX_L4_CSUM, enable);
1652 static int dpaa2_eth_set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
1657 DPNI_OFF_TX_L3_CSUM, enable);
1664 DPNI_OFF_TX_L4_CSUM, enable);
1809 * may still contain some buffers which would enable us
2014 * re-enable data availability notifications
2082 td.enable = !tx_pause;
2083 if (priv->rx_fqtd_enabled == td.enable)
2103 priv->rx_fqtd_enabled = td.enable;
2113 td.enable = !tx_pause || pfc;
2114 if (priv->rx_cgtd_enabled == td.enable)
2130 priv->rx_cgtd_enabled = td.enable;
2561 bool enable;
2565 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2566 err = dpaa2_eth_set_rx_vlan_filtering(priv, enable);
2572 enable = !!(features & NETIF_F_RXCSUM);
2573 err = dpaa2_eth_set_rx_csum(priv, enable);
2579 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
2580 err = dpaa2_eth_set_tx_csum(priv, enable);
3620 /* By default, enable both Rx and Tx pause frames */
4116 dist_cfg.enable = 1;
4148 dist_cfg.enable = 1;