Lines Matching refs:db
226 static void phy_write_1bit(struct uli526x_board_info *db, u32);
227 static u16 phy_read_1bit(struct uli526x_board_info *db);
239 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
241 void __iomem *ioaddr = db->ioaddr;
272 struct uli526x_board_info *db; /* board information structure */
281 dev = alloc_etherdev(sizeof(*db));
316 db = netdev_priv(dev);
321 db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
323 &db->desc_pool_dma_ptr, GFP_KERNEL);
324 if (!db->desc_pool_ptr)
327 db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
329 &db->buf_pool_dma_ptr, GFP_KERNEL);
330 if (!db->buf_pool_ptr)
333 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
334 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
335 db->buf_pool_start = db->buf_pool_ptr;
336 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
340 db->phy.write = phy_writeby_cr10;
341 db->phy.read = phy_readby_cr10;
344 db->phy.write = phy_writeby_cr9;
345 db->phy.read = phy_readby_cr9;
354 db->ioaddr = ioaddr;
355 db->pdev = pdev;
356 db->init = 1;
364 spin_lock_init(&db->lock);
369 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
372 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
392 addr[i] = db->srom[20 + i];
409 pci_iounmap(pdev, db->ioaddr);
412 db->buf_pool_ptr, db->buf_pool_dma_ptr);
416 db->desc_pool_ptr, db->desc_pool_dma_ptr);
431 struct uli526x_board_info *db = netdev_priv(dev);
434 pci_iounmap(pdev, db->ioaddr);
435 dma_free_coherent(&db->pdev->dev,
437 db->desc_pool_ptr, db->desc_pool_dma_ptr);
438 dma_free_coherent(&db->pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
439 db->buf_pool_ptr, db->buf_pool_dma_ptr);
454 struct uli526x_board_info *db = netdev_priv(dev);
459 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
460 db->tx_packet_cnt = 0;
461 db->rx_avail_cnt = 0;
462 db->link_failed = 1;
464 db->wait_reset = 0;
466 db->NIC_capability = 0xf; /* All capability*/
467 db->PHY_reg4 = 0x1e0;
470 db->cr6_data |= ULI526X_TXTH_256;
471 db->cr0_data = CR0_DEFAULT;
476 ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
485 timer_setup(&db->timer, uli526x_timer, 0);
486 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
487 add_timer(&db->timer);
502 struct uli526x_board_info *db = netdev_priv(dev);
503 struct uli_phy_ops *phy = &db->phy;
504 void __iomem *ioaddr = db->ioaddr;
515 uw32(DCR0, db->cr0_data);
519 db->phy_addr = 1;
523 phy_value = phy->read(db, phy_tmp, 3); //peer add
525 db->phy_addr = phy_tmp;
533 db->media_mode = uli526x_media_mode;
536 phy_reg_reset = phy->read(db, db->phy_addr, 0);
538 phy->write(db, db->phy_addr, 0, phy_reg_reset);
545 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
549 uli526x_set_phyxcer(db);
552 if ( !(db->media_mode & ULI526X_AUTO) )
553 db->op_mode = db->media_mode; /* Force Mode */
559 update_cr6(db->cr6_data, ioaddr);
565 db->cr7_data = CR7_DEFAULT;
566 uw32(DCR7, db->cr7_data);
569 uw32(DCR15, db->cr15_data);
572 db->cr6_data |= CR6_RXSC | CR6_TXSC;
573 update_cr6(db->cr6_data, ioaddr);
585 struct uli526x_board_info *db = netdev_priv(dev);
586 void __iomem *ioaddr = db->ioaddr;
602 spin_lock_irqsave(&db->lock, flags);
605 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
606 spin_unlock_irqrestore(&db->lock, flags);
607 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
615 txptr = db->tx_insert_ptr;
620 db->tx_insert_ptr = txptr->next_tx_desc;
623 if (db->tx_packet_cnt < TX_DESC_CNT) {
625 db->tx_packet_cnt++; /* Ready to send */
631 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
635 spin_unlock_irqrestore(&db->lock, flags);
636 uw32(DCR7, db->cr7_data);
652 struct uli526x_board_info *db = netdev_priv(dev);
653 void __iomem *ioaddr = db->ioaddr;
659 del_timer_sync(&db->timer);
664 db->phy.write(db, db->phy_addr, 0, 0x8000);
667 free_irq(db->pdev->irq, dev);
670 uli526x_free_rxbuffer(db);
684 struct uli526x_board_info *db = netdev_priv(dev);
685 void __iomem *ioaddr = db->ioaddr;
688 spin_lock_irqsave(&db->lock, flags);
692 db->cr5_data = ur32(DCR5);
693 uw32(DCR5, db->cr5_data);
694 if ( !(db->cr5_data & 0x180c1) ) {
696 uw32(DCR7, db->cr7_data);
697 spin_unlock_irqrestore(&db->lock, flags);
702 if (db->cr5_data & 0x2000) {
704 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
705 db->reset_fatal++;
706 db->wait_reset = 1; /* Need to RESET */
707 spin_unlock_irqrestore(&db->lock, flags);
712 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
713 uli526x_rx_packet(dev, db);
716 if (db->rx_avail_cnt<RX_DESC_CNT)
720 if ( db->cr5_data & 0x01)
721 uli526x_free_tx_pkt(dev, db);
724 uw32(DCR7, db->cr7_data);
726 spin_unlock_irqrestore(&db->lock, flags);
733 struct uli526x_board_info *db = netdev_priv(dev);
736 uli526x_interrupt(db->pdev->irq, dev);
745 struct uli526x_board_info * db)
750 txptr = db->tx_remove_ptr;
751 while(db->tx_packet_cnt) {
757 db->tx_packet_cnt--;
767 db->tx_fifo_underrun++;
768 if ( !(db->cr6_data & CR6_SFT) ) {
769 db->cr6_data = db->cr6_data | CR6_SFT;
770 update_cr6(db->cr6_data, db->ioaddr);
774 db->tx_excessive_collision++;
776 db->tx_late_collision++;
778 db->tx_no_carrier++;
780 db->tx_loss_carrier++;
782 db->tx_jabber_timeout++;
790 db->tx_remove_ptr = txptr;
793 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
802 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
809 rxptr = db->rx_ready_ptr;
811 while(db->rx_avail_cnt) {
818 db->rx_avail_cnt--;
819 db->interval_rx_cnt++;
821 dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
827 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
845 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
860 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
872 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
879 db->rx_ready_ptr = rxptr;
889 struct uli526x_board_info *db = netdev_priv(dev);
893 spin_lock_irqsave(&db->lock, flags);
897 db->cr6_data |= CR6_PM | CR6_PBF;
898 update_cr6(db->cr6_data, db->ioaddr);
899 spin_unlock_irqrestore(&db->lock, flags);
907 db->cr6_data &= ~(CR6_PM | CR6_PBF);
908 db->cr6_data |= CR6_PAM;
909 spin_unlock_irqrestore(&db->lock, flags);
915 spin_unlock_irqrestore(&db->lock, flags);
919 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
944 cmd->base.phy_address = db->phy_addr;
949 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
953 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
957 if(db->link_failed)
963 if (db->media_mode & ULI526X_AUTO)
1017 struct uli526x_board_info *db = from_timer(db, t, timer);
1018 struct net_device *dev = pci_get_drvdata(db->pdev);
1019 struct uli_phy_ops *phy = &db->phy;
1020 void __iomem *ioaddr = db->ioaddr;
1026 spin_lock_irqsave(&db->lock, flags);
1031 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1032 db->reset_cr8++;
1033 db->wait_reset = 1;
1035 db->interval_rx_cnt = 0;
1038 if ( db->tx_packet_cnt &&
1044 db->reset_TXtimeout++;
1045 db->wait_reset = 1;
1050 if (db->wait_reset) {
1051 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1052 db->reset_count++;
1054 db->timer.expires = ULI526X_TIMER_WUT;
1055 add_timer(&db->timer);
1056 spin_unlock_irqrestore(&db->lock, flags);
1061 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1064 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1069 db->link_failed = 1;
1073 if ( !(db->media_mode & 0x8) )
1074 phy->write(db, db->phy_addr, 0, 0x1000);
1077 if (db->media_mode & ULI526X_AUTO) {
1078 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1079 update_cr6(db->cr6_data, db->ioaddr);
1082 if ((tmp_cr12 & 0x3) && db->link_failed) {
1084 db->link_failed = 0;
1087 if ( (db->media_mode & ULI526X_AUTO) &&
1088 uli526x_sense_speed(db) )
1089 db->link_failed = 1;
1090 uli526x_process_mode(db);
1092 if(db->link_failed==0)
1095 (db->op_mode == ULI526X_100MHF ||
1096 db->op_mode == ULI526X_100MFD)
1098 (db->op_mode == ULI526X_10MFD ||
1099 db->op_mode == ULI526X_100MFD)
1103 /* SHOW_MEDIA_TYPE(db->op_mode); */
1105 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1107 if(db->init==1)
1113 db->init = 0;
1116 db->timer.expires = ULI526X_TIMER_WUT;
1117 add_timer(&db->timer);
1118 spin_unlock_irqrestore(&db->lock, flags);
1130 struct uli526x_board_info *db = netdev_priv(dev);
1131 void __iomem *ioaddr = db->ioaddr;
1134 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1135 update_cr6(db->cr6_data, ioaddr);
1143 uli526x_free_rxbuffer(db);
1146 db->tx_packet_cnt = 0;
1147 db->rx_avail_cnt = 0;
1148 db->link_failed = 1;
1149 db->init=1;
1150 db->wait_reset = 0;
1223 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1228 while (db->rx_avail_cnt) {
1229 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1230 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1231 db->rx_avail_cnt--;
1240 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1242 struct rx_desc *rxptr = db->rx_insert_ptr;
1246 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1250 db->rx_avail_cnt++;
1251 db->rx_insert_ptr = rxptr->next_rx_desc;
1253 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1264 struct uli526x_board_info *db = netdev_priv(dev);
1275 db->tx_insert_ptr = db->first_tx_desc;
1276 db->tx_remove_ptr = db->first_tx_desc;
1277 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1280 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1281 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1282 db->rx_insert_ptr = db->first_rx_desc;
1283 db->rx_ready_ptr = db->first_rx_desc;
1284 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1287 tmp_buf = db->buf_pool_start;
1288 tmp_buf_dma = db->buf_pool_dma_start;
1289 tmp_tx_dma = db->first_tx_desc_dma;
1290 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1301 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1302 tmp_tx->next_tx_desc = db->first_tx_desc;
1305 tmp_rx_dma=db->first_rx_desc_dma;
1306 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1313 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1314 tmp_rx->next_rx_desc = db->first_rx_desc;
1345 struct uli526x_board_info *db = netdev_priv(dev);
1346 void __iomem *ioaddr = db->ioaddr;
1355 txptr = db->tx_insert_ptr;
1384 db->tx_insert_ptr = txptr->next_tx_desc;
1388 if (db->tx_packet_cnt < TX_DESC_CNT) {
1390 db->tx_packet_cnt++;
1392 update_cr6(db->cr6_data | 0x2000, ioaddr);
1394 update_cr6(db->cr6_data, ioaddr);
1408 struct uli526x_board_info *db = netdev_priv(dev);
1412 rxptr = db->rx_insert_ptr;
1414 while(db->rx_avail_cnt < RX_DESC_CNT) {
1419 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1424 db->rx_avail_cnt++;
1427 db->rx_insert_ptr = rxptr;
1435 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1437 void __iomem *ioaddr = db->ioaddr;
1445 srom_clk_write(db, SROM_DATA_1);
1446 srom_clk_write(db, SROM_DATA_1);
1447 srom_clk_write(db, SROM_DATA_0);
1452 srom_clk_write(db, srom_data);
1475 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1477 struct uli_phy_ops *phy = &db->phy;
1481 phy_mode = phy->read(db, db->phy_addr, 1);
1482 phy_mode = phy->read(db, db->phy_addr, 1);
1486 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1497 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1498 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1499 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1500 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1501 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1504 db->op_mode = ULI526X_10MHF;
1519 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1521 struct uli_phy_ops *phy = &db->phy;
1525 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1527 if (db->media_mode & ULI526X_AUTO) {
1529 phy_reg |= db->PHY_reg4;
1532 switch(db->media_mode) {
1543 phy_reg|=db->PHY_reg4;
1544 db->media_mode|=ULI526X_AUTO;
1546 phy->write(db, db->phy_addr, 4, phy_reg);
1549 phy->write(db, db->phy_addr, 0, 0x1200);
1561 static void uli526x_process_mode(struct uli526x_board_info *db)
1563 struct uli_phy_ops *phy = &db->phy;
1567 if (db->op_mode & 0x4)
1568 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1570 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1572 update_cr6(db->cr6_data, db->ioaddr);
1575 if (!(db->media_mode & 0x8)) {
1577 phy_reg = phy->read(db, db->phy_addr, 6);
1581 switch(db->op_mode) {
1587 phy->write(db, db->phy_addr, 0, phy_reg);
1594 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1601 phy_write_1bit(db, PHY_DATA_1);
1604 phy_write_1bit(db, PHY_DATA_0);
1605 phy_write_1bit(db, PHY_DATA_1);
1608 phy_write_1bit(db, PHY_DATA_0);
1609 phy_write_1bit(db, PHY_DATA_1);
1613 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1617 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1620 phy_write_1bit(db, PHY_DATA_1);
1621 phy_write_1bit(db, PHY_DATA_0);
1625 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1628 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1635 phy_write_1bit(db, PHY_DATA_1);
1638 phy_write_1bit(db, PHY_DATA_0);
1639 phy_write_1bit(db, PHY_DATA_1);
1642 phy_write_1bit(db, PHY_DATA_1);
1643 phy_write_1bit(db, PHY_DATA_0);
1647 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1651 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1654 phy_read_1bit(db);
1659 phy_data |= phy_read_1bit(db);
1665 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1668 void __iomem *ioaddr = db->ioaddr;
1683 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1686 void __iomem *ioaddr = db->ioaddr;
1698 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1700 void __iomem *ioaddr = db->ioaddr;
1715 static u16 phy_read_1bit(struct uli526x_board_info *db)
1717 void __iomem *ioaddr = db->ioaddr;