Lines Matching defs:uw32
35 #define uw32(reg, val) iowrite32(val, ioaddr + (reg))
243 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
245 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
247 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
374 uw32(DCR0, 0x10000); //Diagnosis mode
375 uw32(DCR13, 0x1c0); //Reset dianostic pointer port
376 uw32(DCR14, 0); //Clear reset port
377 uw32(DCR14, 0x10); //Reset ID Table pointer
378 uw32(DCR14, 0); //Clear reset port
379 uw32(DCR13, 0); //Clear CR13
380 uw32(DCR13, 0x1b0); //Select ID Table access port
385 uw32(DCR13, 0); //Clear CR13
386 uw32(DCR0, 0); //Clear CR0
513 uw32(DCR0, ULI526X_RESET); /* RESET MAC */
515 uw32(DCR0, db->cr0_data);
566 uw32(DCR7, db->cr7_data);
569 uw32(DCR15, db->cr15_data);
612 uw32(DCR7, 0);
626 uw32(DCR1, 0x1); /* Issue Tx polling */
636 uw32(DCR7, db->cr7_data);
662 uw32(DCR0, ULI526X_RESET);
689 uw32(DCR7, 0);
693 uw32(DCR5, db->cr5_data);
696 uw32(DCR7, db->cr7_data);
724 uw32(DCR7, db->cr7_data);
1040 uw32(DCR1, 0x1); // Tx polling again
1136 uw32(DCR7, 0); /* Disable Interrupt */
1137 uw32(DCR5, ur32(DCR5));
1277 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1284 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1327 uw32(DCR6, cr6_data);
1393 uw32(DCR1, 0x1); /* Issue Tx polling */
1441 uw32(DCR9, CR9_SROM_READ);
1442 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1455 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1458 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1462 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1466 uw32(DCR9, CR9_SROM_READ);
1673 uw32(DCR10, cr10_value);
1691 uw32(DCR10, cr10_value);
1702 uw32(DCR9, data); /* MII Clock Low */
1704 uw32(DCR9, data | MDCLKH); /* MII Clock High */
1706 uw32(DCR9, data); /* MII Clock Low */
1720 uw32(DCR9, 0x50000);
1723 uw32(DCR9, 0x40000);