Lines Matching refs:db
354 struct dmfe_board_info *db; /* board information structure */
378 dev = alloc_etherdev(sizeof(*db));
422 db = netdev_priv(dev);
425 db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
427 &db->desc_pool_dma_ptr, GFP_KERNEL);
428 if (!db->desc_pool_ptr) {
433 db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
435 &db->buf_pool_dma_ptr, GFP_KERNEL);
436 if (!db->buf_pool_ptr) {
441 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
442 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
443 db->buf_pool_start = db->buf_pool_ptr;
444 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
446 db->chip_id = ent->driver_data;
448 db->ioaddr = pci_iomap(pdev, 0, 0);
449 if (!db->ioaddr) {
454 db->chip_revision = pdev->revision;
455 db->wol_mode = 0;
457 db->pdev = pdev;
463 spin_lock_init(&db->lock);
467 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
468 db->chip_type = 1; /* DM9102A E3 */
470 db->chip_type = 0;
474 ((__le16 *) db->srom)[i] =
475 cpu_to_le16(read_srom_word(db->ioaddr, i));
479 eth_hw_addr_set(dev, &db->srom[20]);
494 pci_iounmap(pdev, db->ioaddr);
497 db->buf_pool_ptr, db->buf_pool_dma_ptr);
501 db->desc_pool_ptr, db->desc_pool_dma_ptr);
516 struct dmfe_board_info *db = netdev_priv(dev);
523 pci_iounmap(db->pdev, db->ioaddr);
524 dma_free_coherent(&db->pdev->dev,
526 db->desc_pool_ptr, db->desc_pool_dma_ptr);
527 dma_free_coherent(&db->pdev->dev,
529 db->buf_pool_ptr, db->buf_pool_dma_ptr);
545 struct dmfe_board_info *db = netdev_priv(dev);
546 const int irq = db->pdev->irq;
556 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
557 db->tx_packet_cnt = 0;
558 db->tx_queue_cnt = 0;
559 db->rx_avail_cnt = 0;
560 db->wait_reset = 0;
562 db->first_in_callback = 0;
563 db->NIC_capability = 0xf; /* All capability*/
564 db->PHY_reg4 = 0x1e0;
567 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
568 (db->chip_revision >= 0x30) ) {
569 db->cr6_data |= DMFE_TXTH_256;
570 db->cr0_data = CR0_DEFAULT;
571 db->dm910x_chk_mode=4; /* Enter the normal mode */
573 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
574 db->cr0_data = 0;
575 db->dm910x_chk_mode = 1; /* Enter the check mode */
585 timer_setup(&db->timer, dmfe_timer, 0);
586 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
587 add_timer(&db->timer);
602 struct dmfe_board_info *db = netdev_priv(dev);
603 void __iomem *ioaddr = db->ioaddr;
610 dw32(DCR0, db->cr0_data);
614 db->phy_addr = 1;
617 dmfe_parse_srom(db);
618 db->media_mode = dmfe_media_mode;
622 if (db->chip_id == PCI_DM9009_ID) {
629 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
630 dmfe_set_phyxcer(db);
633 if ( !(db->media_mode & DMFE_AUTO) )
634 db->op_mode = db->media_mode; /* Force Mode */
640 update_cr6(db->cr6_data, ioaddr);
643 if (db->chip_id == PCI_DM9132_ID)
649 db->cr7_data = CR7_DEFAULT;
650 dw32(DCR7, db->cr7_data);
653 dw32(DCR15, db->cr15_data);
656 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
657 update_cr6(db->cr6_data, ioaddr);
669 struct dmfe_board_info *db = netdev_priv(dev);
670 void __iomem *ioaddr = db->ioaddr;
686 spin_lock_irqsave(&db->lock, flags);
689 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
690 spin_unlock_irqrestore(&db->lock, flags);
691 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
699 txptr = db->tx_insert_ptr;
704 db->tx_insert_ptr = txptr->next_tx_desc;
707 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
709 db->tx_packet_cnt++; /* Ready to send */
713 db->tx_queue_cnt++; /* queue TX packet */
718 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
722 spin_unlock_irqrestore(&db->lock, flags);
723 dw32(DCR7, db->cr7_data);
739 struct dmfe_board_info *db = netdev_priv(dev);
740 void __iomem *ioaddr = db->ioaddr;
748 del_timer_sync(&db->timer);
753 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
756 free_irq(db->pdev->irq, dev);
759 dmfe_free_rxbuffer(db);
764 db->tx_fifo_underrun, db->tx_excessive_collision,
765 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
766 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
767 db->reset_fatal, db->reset_TXtimeout);
782 struct dmfe_board_info *db = netdev_priv(dev);
783 void __iomem *ioaddr = db->ioaddr;
788 spin_lock_irqsave(&db->lock, flags);
791 db->cr5_data = dr32(DCR5);
792 dw32(DCR5, db->cr5_data);
793 if ( !(db->cr5_data & 0xc1) ) {
794 spin_unlock_irqrestore(&db->lock, flags);
802 if (db->cr5_data & 0x2000) {
804 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
805 db->reset_fatal++;
806 db->wait_reset = 1; /* Need to RESET */
807 spin_unlock_irqrestore(&db->lock, flags);
812 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
813 dmfe_rx_packet(dev, db);
816 if (db->rx_avail_cnt<RX_DESC_CNT)
820 if ( db->cr5_data & 0x01)
821 dmfe_free_tx_pkt(dev, db);
824 if (db->dm910x_chk_mode & 0x2) {
825 db->dm910x_chk_mode = 0x4;
826 db->cr6_data |= 0x100;
827 update_cr6(db->cr6_data, ioaddr);
831 dw32(DCR7, db->cr7_data);
833 spin_unlock_irqrestore(&db->lock, flags);
847 struct dmfe_board_info *db = netdev_priv(dev);
848 const int irq = db->pdev->irq;
862 static void dmfe_free_tx_pkt(struct net_device *dev, struct dmfe_board_info *db)
865 void __iomem *ioaddr = db->ioaddr;
868 txptr = db->tx_remove_ptr;
869 while(db->tx_packet_cnt) {
875 db->tx_packet_cnt--;
886 db->tx_fifo_underrun++;
887 if ( !(db->cr6_data & CR6_SFT) ) {
888 db->cr6_data = db->cr6_data | CR6_SFT;
889 update_cr6(db->cr6_data, ioaddr);
893 db->tx_excessive_collision++;
895 db->tx_late_collision++;
897 db->tx_no_carrier++;
899 db->tx_loss_carrier++;
901 db->tx_jabber_timeout++;
909 db->tx_remove_ptr = txptr;
912 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
914 db->tx_packet_cnt++; /* Ready to send */
915 db->tx_queue_cnt--;
921 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
944 static void dmfe_rx_packet(struct net_device *dev, struct dmfe_board_info *db)
951 rxptr = db->rx_ready_ptr;
953 while(db->rx_avail_cnt) {
958 db->rx_avail_cnt--;
959 db->interval_rx_cnt++;
961 dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
968 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
986 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
990 if ( (db->dm910x_chk_mode & 1) &&
994 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
995 db->dm910x_chk_mode = 3;
1009 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1021 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1028 db->rx_ready_ptr = rxptr;
1037 struct dmfe_board_info *db = netdev_priv(dev);
1042 spin_lock_irqsave(&db->lock, flags);
1046 db->cr6_data |= CR6_PM | CR6_PBF;
1047 update_cr6(db->cr6_data, db->ioaddr);
1048 spin_unlock_irqrestore(&db->lock, flags);
1054 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1055 db->cr6_data |= CR6_PAM;
1056 spin_unlock_irqrestore(&db->lock, flags);
1061 if (db->chip_id == PCI_DM9132_ID)
1065 spin_unlock_irqrestore(&db->lock, flags);
1084 struct dmfe_board_info *db = netdev_priv(dev);
1090 db->wol_mode = wolinfo->wolopts;
1097 struct dmfe_board_info *db = netdev_priv(dev);
1100 wolinfo->wolopts = db->wol_mode;
1118 struct dmfe_board_info *db = from_timer(db, t, timer);
1119 struct net_device *dev = pci_get_drvdata(db->pdev);
1120 void __iomem *ioaddr = db->ioaddr;
1128 spin_lock_irqsave(&db->lock, flags);
1131 if (db->first_in_callback == 0) {
1132 db->first_in_callback = 1;
1133 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1134 db->cr6_data &= ~0x40000;
1135 update_cr6(db->cr6_data, ioaddr);
1136 dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1137 db->cr6_data |= 0x40000;
1138 update_cr6(db->cr6_data, ioaddr);
1139 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1140 add_timer(&db->timer);
1141 spin_unlock_irqrestore(&db->lock, flags);
1148 if ( (db->dm910x_chk_mode & 0x1) &&
1150 db->dm910x_chk_mode = 0x4;
1154 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1155 db->reset_cr8++;
1156 db->wait_reset = 1;
1158 db->interval_rx_cnt = 0;
1161 if ( db->tx_packet_cnt &&
1167 db->reset_TXtimeout++;
1168 db->wait_reset = 1;
1173 if (db->wait_reset) {
1174 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1175 db->reset_count++;
1177 db->first_in_callback = 0;
1178 db->timer.expires = DMFE_TIMER_WUT;
1179 add_timer(&db->timer);
1180 spin_unlock_irqrestore(&db->lock, flags);
1185 if (db->chip_id == PCI_DM9132_ID)
1190 if ( ((db->chip_id == PCI_DM9102_ID) &&
1191 (db->chip_revision == 0x30)) ||
1192 ((db->chip_id == PCI_DM9132_ID) &&
1193 (db->chip_revision == 0x10)) ) {
1212 dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1213 link_ok_phy = (dmfe_phy_read (db->ioaddr,
1214 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1228 if ( !(db->media_mode & 0x38) )
1229 dmfe_phy_write(db->ioaddr, db->phy_addr,
1230 0, 0x1000, db->chip_id);
1233 if (db->media_mode & DMFE_AUTO) {
1235 db->cr6_data|=0x00040000; /* bit18=1, MII */
1236 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1237 update_cr6(db->cr6_data, ioaddr);
1244 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1246 SHOW_MEDIA_TYPE(db->op_mode);
1249 dmfe_process_mode(db);
1253 if (db->HPNA_command & 0xf00) {
1254 db->HPNA_timer--;
1255 if (!db->HPNA_timer)
1256 dmfe_HPNA_remote_cmd_chk(db);
1260 db->timer.expires = DMFE_TIMER_WUT;
1261 add_timer(&db->timer);
1262 spin_unlock_irqrestore(&db->lock, flags);
1276 struct dmfe_board_info *db = netdev_priv(dev);
1277 void __iomem *ioaddr = db->ioaddr;
1282 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1283 update_cr6(db->cr6_data, ioaddr);
1291 dmfe_free_rxbuffer(db);
1294 db->tx_packet_cnt = 0;
1295 db->tx_queue_cnt = 0;
1296 db->rx_avail_cnt = 0;
1298 db->wait_reset = 0;
1312 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1317 while (db->rx_avail_cnt) {
1318 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1319 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1320 db->rx_avail_cnt--;
1329 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1331 struct rx_desc *rxptr = db->rx_insert_ptr;
1335 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
1339 db->rx_avail_cnt++;
1340 db->rx_insert_ptr = rxptr->next_rx_desc;
1342 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1353 struct dmfe_board_info *db = netdev_priv(dev);
1354 void __iomem *ioaddr = db->ioaddr;
1365 db->tx_insert_ptr = db->first_tx_desc;
1366 db->tx_remove_ptr = db->first_tx_desc;
1367 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1370 db->first_rx_desc = (void *)db->first_tx_desc +
1373 db->first_rx_desc_dma = db->first_tx_desc_dma +
1375 db->rx_insert_ptr = db->first_rx_desc;
1376 db->rx_ready_ptr = db->first_rx_desc;
1377 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1380 tmp_buf = db->buf_pool_start;
1381 tmp_buf_dma = db->buf_pool_dma_start;
1382 tmp_tx_dma = db->first_tx_desc_dma;
1383 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1394 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1395 tmp_tx->next_tx_desc = db->first_tx_desc;
1398 tmp_rx_dma=db->first_rx_desc_dma;
1399 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1406 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1407 tmp_rx->next_rx_desc = db->first_rx_desc;
1439 struct dmfe_board_info *db = netdev_priv(dev);
1440 void __iomem *ioaddr = db->ioaddr + 0xc0;
1476 struct dmfe_board_info *db = netdev_priv(dev);
1485 txptr = db->tx_insert_ptr;
1514 db->tx_insert_ptr = txptr->next_tx_desc;
1518 if (!db->tx_packet_cnt) {
1519 void __iomem *ioaddr = db->ioaddr;
1522 db->tx_packet_cnt++;
1524 update_cr6(db->cr6_data | 0x2000, ioaddr);
1526 update_cr6(db->cr6_data, ioaddr);
1529 db->tx_queue_cnt++; /* Put in TX queue */
1540 struct dmfe_board_info *db = netdev_priv(dev);
1544 rxptr = db->rx_insert_ptr;
1546 while(db->rx_avail_cnt < RX_DESC_CNT) {
1550 rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb->data,
1555 db->rx_avail_cnt++;
1558 db->rx_insert_ptr = rxptr;
1622 static u8 dmfe_sense_speed(struct dmfe_board_info *db)
1624 void __iomem *ioaddr = db->ioaddr;
1629 update_cr6(db->cr6_data & ~0x40000, ioaddr);
1631 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1632 phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1635 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1636 phy_mode = dmfe_phy_read(db->ioaddr,
1637 db->phy_addr, 7, db->chip_id) & 0xf000;
1639 phy_mode = dmfe_phy_read(db->ioaddr,
1640 db->phy_addr, 17, db->chip_id) & 0xf000;
1642 case 0x1000: db->op_mode = DMFE_10MHF; break;
1643 case 0x2000: db->op_mode = DMFE_10MFD; break;
1644 case 0x4000: db->op_mode = DMFE_100MHF; break;
1645 case 0x8000: db->op_mode = DMFE_100MFD; break;
1646 default: db->op_mode = DMFE_10MHF;
1651 db->op_mode = DMFE_10MHF;
1666 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1668 void __iomem *ioaddr = db->ioaddr;
1672 db->cr6_data &= ~0x40000;
1673 update_cr6(db->cr6_data, ioaddr);
1676 if (db->chip_id == PCI_DM9009_ID) {
1677 phy_reg = dmfe_phy_read(db->ioaddr,
1678 db->phy_addr, 18, db->chip_id) & ~0x1000;
1680 dmfe_phy_write(db->ioaddr,
1681 db->phy_addr, 18, phy_reg, db->chip_id);
1685 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1687 if (db->media_mode & DMFE_AUTO) {
1689 phy_reg |= db->PHY_reg4;
1692 switch(db->media_mode) {
1698 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1703 phy_reg|=db->PHY_reg4;
1704 db->media_mode|=DMFE_AUTO;
1706 dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1709 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1710 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1711 if ( !db->chip_type )
1712 dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1723 static void dmfe_process_mode(struct dmfe_board_info *db)
1728 if (db->op_mode & 0x4)
1729 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1731 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1734 if (db->op_mode & 0x10) /* 1M HomePNA */
1735 db->cr6_data |= 0x40000;/* External MII select */
1737 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1739 update_cr6(db->cr6_data, db->ioaddr);
1742 if ( !(db->media_mode & 0x18)) {
1744 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1748 switch(db->op_mode) {
1754 dmfe_phy_write(db->ioaddr,
1755 db->phy_addr, 0, phy_reg, db->chip_id);
1756 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1758 dmfe_phy_write(db->ioaddr,
1759 db->phy_addr, 0, phy_reg, db->chip_id);
1901 static void dmfe_parse_srom(struct dmfe_board_info * db)
1903 char * srom = db->srom;
1909 db->cr15_data = CR15_DEFAULT;
1915 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1916 db->PHY_reg4 = 0;
1918 switch( db->NIC_capability & tmp_reg ) {
1919 case 0x1: db->PHY_reg4 |= 0x0020; break;
1920 case 0x2: db->PHY_reg4 |= 0x0040; break;
1921 case 0x4: db->PHY_reg4 |= 0x0080; break;
1922 case 0x8: db->PHY_reg4 |= 0x0100; break;
1940 db->cr15_data |= 0x40;
1944 db->cr15_data |= 0x400;
1948 db->cr15_data |= 0x9800;
1952 db->HPNA_command = 1;
1956 db->HPNA_command |= 0x8000;
1961 case 0: db->HPNA_command |= 0x0904; break;
1962 case 1: db->HPNA_command |= 0x0a00; break;
1963 case 2: db->HPNA_command |= 0x0506; break;
1964 case 3: db->HPNA_command |= 0x0602; break;
1968 case 0: db->HPNA_command |= 0x0004; break;
1969 case 1: db->HPNA_command |= 0x0000; break;
1970 case 2: db->HPNA_command |= 0x0006; break;
1971 case 3: db->HPNA_command |= 0x0002; break;
1975 db->HPNA_present = 0;
1976 update_cr6(db->cr6_data | 0x40000, db->ioaddr);
1977 tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1980 db->HPNA_timer = 8;
1981 if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1983 db->HPNA_present = 1;
1984 dmfe_program_DM9801(db, tmp_reg);
1987 db->HPNA_present = 2;
1988 dmfe_program_DM9802(db);
1999 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2006 db->HPNA_command |= 0x1000;
2007 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2009 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2012 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2014 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2020 db->HPNA_command |= 0x1000;
2021 reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2023 reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2027 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2028 dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2029 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2037 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2042 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2043 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2045 dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2054 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2059 phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2068 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2069 dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2070 db->chip_id);
2071 db->HPNA_timer=8;
2073 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2090 struct dmfe_board_info *db = netdev_priv(dev);
2091 void __iomem *ioaddr = db->ioaddr;
2097 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2098 update_cr6(db->cr6_data, ioaddr);
2105 dmfe_free_rxbuffer(db);