Lines Matching defs:adapter
11 adapter_t *adapter;
59 struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p)
66 tp->adapter = adapter;
73 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
76 if (!t1_is_asic(tp->adapter)) {
79 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
81 tp->adapter->regs + A_PL_ENABLE);
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
88 tp->adapter->regs + A_PL_ENABLE);
94 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
97 if (!t1_is_asic(tp->adapter)) {
99 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
101 tp->adapter->regs + A_PL_ENABLE);
105 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
107 tp->adapter->regs + A_PL_ENABLE);
114 if (!t1_is_asic(tp->adapter)) {
116 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
117 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
121 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
122 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
131 if (!t1_is_asic(tp->adapter))
135 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
136 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
142 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
148 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
167 adapter_t *adapter = tp->adapter;
169 tp_init(adapter, p, tp_clk);
170 writel(F_TP_RESET, adapter->regs + A_TP_RESET);